Multi-Output LDO Regulator for Clock Skew Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Clock skew occurs in electronic devices due to voltage changes in clock generating circuits, leading to potential malfunctions such as communication errors, which existing LDO regulators fail to adequately address.

Innovation Solution

A low dropout (LDO) regulator generates multiple output voltages corresponding to a reference voltage, using an amplifier to create an error voltage and a trimming control circuit to generate trimming signals, which are used by an output buffer to maintain consistent voltage levels across multiple clock signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional LDO regulator applies a single output voltage through an output buffer, then the circuit structure is simple, but voltage changes occur due to current consumption and internal resistance causing clock skew

Engineering Contradiction:
Improveclock signal accuracyVSAvoidLDO regulator structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the single output voltage into multiple output voltages (first output voltage, second output voltage, etc.) corresponding to different clock signals. Each output voltage is independently controlled through separate trimming signals, allowing individual adjustment to compensate for voltage drops and eliminate clock skew between different clock signals.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different trimming signals to different output voltages based on their specific requirements. Each output voltage receives a customized trimming signal tailored to its particular voltage drop characteristics, enabling precise local adjustment rather than uniform control across all outputs.

Inventive Principle:
Principle #3Local quality

2Reliability

If multiple output voltages are applied to clock generating circuit through output buffer, then clock skew is reduced, but voltage consistency becomes difficult to maintain

Engineering Contradiction:
Improveclock signal synchronizationVSAvoidvoltage level consistency
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent employs trimming control circuits that generate trimming signals based on feedback from the actual output voltages. These trimming signals are adjusted to compensate for voltage variations, ensuring that each output voltage maintains its intended level despite variations in current consumption and internal resistance.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent dynamically adjusts the trimming signals to change the voltage parameters of each output voltage. By modifying the trimming signal levels, the system compensates for voltage drops and maintains consistent voltage levels across multiple outputs, addressing the precision requirement.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If trimming signals are generated based on output voltages, then voltage accuracy is improved, but control circuit complexity increases

Engineering Contradiction:
Improveoutput voltage accuracyVSAvoidtrimming control circuit
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent generates trimming signals in advance based on the required output voltage levels and applies them to the output buffer before the actual voltage regulation occurs. This preliminary adjustment ensures that the output voltages are accurately established from the start, reducing the need for complex real-time control mechanisms.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12411512B2Low dropout regulator, clock generating circuit, and memory device
Publication Date: 2025.09.09 SAMSUNG ELECTRONICS CO LTD
  • US12411512B2 patent drawing
  • US12411512B2 patent drawing
  • US12411512B2 patent drawing

AI summary

A low dropout (LDO) regulator is configured to generate first to nth output voltages, where n is a natural number greater than or equal to 2, and each of the first to nth output voltages corresponds to a reference voltage. The LDO regulator includes an amplifier configured to generate an error voltage based on the reference voltage and a first output voltage of the first to nth output voltages, a trimming control circuit configured to generate first to (n−1)th trimming signals based on the first to nth output voltages, and an output buffer circuit configured to generate the first to nth output voltages based on the error voltage and the first to (n−1)th trimming signals.