Multi-Output Logic Cells for Chip Area and Power Reduction
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Solution Overview
Problem
In cell-based digital semiconductor chip design, complex multi-stage cells are often decomposed into simpler cells due to limitations in sharing subexpressions and fixed drive strength ratios, leading to increased area and power consumption.
Innovation Solution
The introduction of a new class of multi-output cells that expose intermediate outputs, allowing for shared logic and incremental changes in cell mapping, enabling more efficient power usage and area reduction by replacing multiple circuit elements with these cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If complex multi-stage cells are decomposed into simpler cells, then the design can be implemented using standard library cells, but the area and power consumption increase
Solution Approach 1:
The patent combines multiple simpler cells into a single complex multi-stage cell that implements multiple logic functions (e.g., AND, OR, NAND, NOR) with shared subexpressions. By merging these functions into one cell, the chip area is reduced compared to using separate cells for each function, while maintaining implementability through systematic construction methods.
Solution Approach 2:
The complex multi-stage cell is designed to perform multiple logic functions simultaneously through shared subexpressions. For example, a single cell can implement both AND and OR functions by sharing common logic paths, making the cell universal and reducing the overall area required for implementing multiple functions.
2Ease of manufacture
If complex multi-stage cells are decomposed into simpler cells, then the design can be implemented using standard library cells, but the power consumption increases
Solution Approach 1:
By merging multiple logic functions into a single complex cell with shared subexpressions, the patent reduces the total number of cell instances required. This reduction in cell count directly lowers power consumption, as fewer cells mean less dynamic switching activity and lower overall energy usage while maintaining implementability.
3Ease of manufacture
If multiple cells are used to implement logic functions, then the design is easier to implement with standard libraries, but the area increases
Solution Approach 1:
The complex multi-stage cell is designed as a universal building block that can implement multiple logic functions through shared subexpressions. This multi-functionality allows a single cell type to replace multiple separate cell instances, reducing chip area while maintaining the ease of implementation through standardized cell-based design methodologies.
4Device complexity
If simple single-output cells are used, then the cell library is easier to manage, but the area and power efficiency decrease
Solution Approach 1:
The patent merges multiple single-output cells into complex multi-stage cells with multiple outputs that share subexpressions. While this increases individual cell complexity, it reduces the total number of cells required in the design, improving area efficiency. The systematic construction methods keep the cell library manageable despite the increased complexity of individual cells.
Data Source
AI summary
A method includes receiving a design file for a circuit design and receiving a library that defines a cell that includes one or more inputs, a first combinational logic circuit element, a second combinational logic circuit element, a first output, and a second output. The method also includes replacing a plurality of circuit elements in the circuit design with the cell and compiling the circuit design after replacing the plurality of circuit elements with the cell. The first and second outputs of the cell in the compiled circuit design replace a plurality of outputs of the plurality of circuit elements.