Multi-Output LUT Memory Cell for Lower-Area Coarse-Grained FPGA Logic
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Solution Overview
Problem
The high cost and inefficiencies of transitioning from Field Programmable Gate Arrays (FPGAs) to Application Specific ICs (ASICs) and Customer-Owned Tooling (COT) chips, particularly in advanced semiconductor technology nodes, hinder innovation and scalability due to larger chip size, higher fabrication costs, and increased Non-Recurring Engineering (NRE) expenses.
Innovation Solution
A multichip package comprising standardized commodity FPGA IC chips and non-volatile memory IC chips, allowing for field programming and configuration through software, reducing NRE costs and enabling innovation in advanced technology nodes by using a standardized commodity logic drive as an alternative to ASICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA is used for implementation, then flexibility and reconfigurability are improved, but chip size, fabrication cost, and power consumption increase
Solution Approach 1:
The patent divides the FPGA chip into multiple coarse-grained reconfigurable units (CGRUs) that can be independently configured. Each CGRU handles specific computational tasks, allowing the chip to maintain flexibility while reducing the overall area required by eliminating redundant fine-grained logic elements and interconnect structures.
Solution Approach 2:
The patent implements universal CGRUs that can be configured to perform multiple different computational functions through reconfiguration. Each CGRU can adapt its internal logic and data paths to execute various algorithms, providing FPGA-like versatility with a more compact and efficient architecture that reduces chip size compared to traditional FPGAs.
2Adaptability or versatility
If FPGA is used for implementation, then flexibility and reconfigurability are improved, but fabrication cost increases
Solution Approach 1:
The patent segments the FPGA architecture into standardized CGRU blocks that can be efficiently manufactured using standard cell libraries and automated place-and-route tools. This segmentation enables better utilization of fabrication capacity and reduces non-recurring engineering (NRE) costs compared to custom ASIC designs, while maintaining flexibility through reconfiguration capabilities.
Solution Approach 2:
The patent changes the architectural parameters from fine-grained to coarse-grained reconfiguration, which simplifies the manufacturing process. The CGRUs use standardized logic elements and interconnect patterns that are easier to manufacture at scale, reducing fabrication complexity and cost while still providing adequate flexibility for various applications.
3Adaptability or versatility
If FPGA is used for implementation, then flexibility and reconfigurability are improved, but power consumption increases
Solution Approach 1:
The patent divides the FPGA into discrete CGRU segments that can be independently powered or clocked. Only the actively used CGRUs consume significant power, reducing overall power consumption compared to traditional FPGAs where the entire chip remains active. This segmentation enables power management strategies that deactivate unused portions of the device.
Solution Approach 2:
The patent extracts and eliminates redundant logic elements, interconnect resources, and support circuits from the traditional FPGA architecture that contribute to high power consumption. The CGRU design uses minimal necessary components to achieve reconfigurability, significantly reducing the static and dynamic power consumption while maintaining flexibility for various computational tasks.
4Productivity
If ASIC or COT chip is used for implementation, then performance is improved, but NRE cost increases greatly
Solution Approach 1:
The patent implements a dynamically reconfigurable architecture with CGRUs that can adapt their configuration at runtime based on the workload requirements. This dynamic capability allows the device to achieve ASIC-like performance for specific tasks while maintaining the flexibility of FPGAs, and can be manufactured with lower NRE costs using standard FPGA fabrication processes rather than custom ASIC manufacturing.
Solution Approach 2:
The patent changes the reconfiguration granularity parameter from fine-grained to coarse-grained, which enables better performance for data-parallel workloads while reducing manufacturing complexity. The CGRU architecture with standardized blocks and simplified interconnect can be manufactured using standard FPGA processes, achieving ASIC-like performance at fraction of the NRE cost by avoiding custom mask sets and specialized fabrication procedures.
Data Source
AI summary
A semiconductor integrated-circuit (IC) chip comprises a memory cell including: a latch circuit comprising first and second inverters coupling to each other, a first latch node coupling to an input point of the first inverter and an output point of the second inverter and a second latch node coupling to an input point of the second inverter and an output point of the first inverter; a first N-type MOS transistor having a first terminal coupling to the first latch node, a second terminal coupling to a first output point of the memory cell, and a first gate terminal for controlling coupling between the first latch node and the first output point of the memory cell; a second N-type MOS transistor having a third terminal coupling to the second latch node, a fourth terminal coupling to a second output point of the memory cell, and a second gate terminal for controlling coupling between the second latch node and the second output point of the memory cell; and a P-type MOS transistor having a fifth terminal coupling to the first latch node, a sixth terminal coupling to a third output point of the memory cell, and a third gate terminal for controlling coupling between the first latch node and the third output point of the memory cell.