Multi-Output PLL Frequency Control for Independent Clock Correction
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Solution Overview
Problem
Modern communications devices face challenges in maintaining accurate and stable clock frequencies across multiple communication blocks due to shared reference clocks, leading to performance impairments from AFC corrections and Doppler shift-induced frequency variations.
Innovation Solution
The use of phase-locked loop circuits to generate multiple clock signals from a single reference clock, with independent frequency correction mechanisms for each signal, allowing for proportional adjustments to the frequency-division ratios and the reference clock to maintain stability and accuracy without disrupting other circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a shared reference clock is used to synthesize clock signals for multiple communication blocks, then cost is minimized, but frequency stability and accuracy are degraded due to AFC corrections and Doppler shift-induced variations affecting all circuits
Solution Approach 1:
The patent divides the frequency correction function into separate segments for each communication block. Each PLL circuit has its own independent frequency correction mechanism that operates autonomously on its output signal without affecting other blocks. This segmentation allows each circuit to maintain its required frequency stability independently while still using the shared reference clock, thereby resolving the contradiction between cost minimization and frequency stability maintenance.
2Measurement precision
If AFC techniques are used to correct frequency errors in one communication block, then frequency accuracy is improved, but other circuits sharing the reference clock experience performance impairments due to reference frequency variations
Solution Approach 1:
The patent extracts the frequency correction function from the shared reference clock and applies it independently to each PLL output signal. By taking out the correction mechanism from the common reference and applying it separately to each block's output, the system achieves high frequency accuracy for each block without causing harmful frequency variations to propagate to other circuits sharing the reference clock.
3Adaptability or versatility
If the reference clock frequency is adjusted to correct Doppler shift errors, then cellular transceiver frequency tracking is improved, but GPS receiver and other reference-dependent circuits experience disruptions during critical measurement intervals
Solution Approach 1:
The patent applies local quality by making each PLL circuit's frequency correction local to its own output signal rather than globally affecting the reference clock. Each communication block receives frequency corrections tailored to its specific requirements (e.g., Doppler compensation for cellular, high stability for GPS) without interfering with other blocks. This local application of quality ensures that frequency tracking adaptability is achieved without disrupting critical measurements in other circuits.
Data Source
AI summary
Methods and circuits for synthesizing two or more signals phase-locked to a common reference frequency signal are disclosed. In one embodiment, a method comprises generating first and second output signals phase-locked to a reference clock signal, using first and second phase-locked loop circuits. In response to a detected frequency error in the first output signal, the first output signal is corrected by adjusting a frequency-division ratio in the first phase-locked loop circuit. The second output signal is corrected, separately from the correction to the first output signal, by adjusting a frequency-division ratio in the second phase-locked loop circuit, using an adjustment parameter calculated from the detected frequency error. In another exemplary method, first and second output signals are generated as described above, using first and second phase-locked loop circuits. The first output signal is corrected by adjusting a frequency-division ratio in the first phase-locked loop circuit and generating a control signal to adjust the frequency of the reference clock signal, in response to detected frequency error in the first output signal. Because the second output signal is derived from the common reference clock signal, adjustments to the reference clock frequency will also adjust the frequency of the second output signal. Additional adjustments to the second output signal may be applied in some embodiments by adjusting a frequency-division ratio in the second phase-locked loop circuits. Circuits for implementing the described methods are also disclosed.