Multi-Oxide Semiconductor Channel With Ti Layer for Low-Resistance Contacts
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Solution Overview
Problem
Oxide semiconductors have lower carrier mobility than silicon, leading to higher resistance and lower driving ability in transistors, making them unsuitable for high-integration and high-performance semiconductor devices.
Innovation Solution
A semiconductor device with a multi-oxide semiconductor channel and a Ti-based metal layer that scavenges oxygen vacancies to increase carrier concentration, combined with a specific layer structure including a fin-type insulating pattern, metal layers, and a gate electrode configuration, enhancing conductivity and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an oxide semiconductor channel is used, then off-characteristics are improved, but carrier mobility is reduced leading to higher resistance and lower driving ability
Solution Approach 1:
The patent applies local quality by creating different oxide semiconductor layers with distinct compositions and properties: a first oxide semiconductor layer with higher carrier concentration for low resistance, and a second oxide semiconductor layer with appropriate mobility characteristics. This layered structure allows different regions to optimize for their specific functions, resolving the contradiction between low off-current and high driving ability.
Solution Approach 2:
The patent uses composite materials by combining multiple oxide semiconductor layers with different compositions (e.g., In-Ga-Zn-O with varying ratios) to create a channel structure that exhibits both low off-current characteristics and high carrier mobility. The composite structure leverages the complementary properties of each layer to achieve both reliability and power performance.
2Reliability
If an oxide semiconductor channel is used, then off-characteristics are improved, but resistance increases
Solution Approach 1:
The patent applies local quality by creating different oxide semiconductor layers with distinct compositions and properties: a first oxide semiconductor layer with higher carrier concentration for low resistance, and a second oxide semiconductor layer with appropriate mobility characteristics. This layered structure allows different regions to optimize for their specific functions, resolving the contradiction between low off-current and high driving ability.
Solution Approach 2:
The patent changes physical parameters by controlling the composition ratios (e.g., In:Ga:Zn:O ratios), thicknesses, and crystalline structures of different oxide semiconductor layers. By adjusting these parameters, the patent achieves optimal balance between carrier concentration (affecting resistance) and off-current characteristics, transforming the material properties to resolve the contradiction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the driving capability of transistors by lowering electrical resistance and off-current, while maintaining low contact resistance, thus enabling better performance in high-integration semiconductor devices.
Implementation Method 1
A semiconductor device with a multi-oxide semiconductor channel and a Ti-based metal layer that scavenges oxygen vacancies to increase carrier concentration
Data Source
AI summary
A semiconductor device include a substrate having a gate area and a contact area, a buried insulating layer formed over the substrate, a fin-type insulating pattern formed over the buried insulating layer and extending in a first horizontal direction, a lower metal layer covering an upper surface and side surfaces of the fin-type insulating pattern in the contact pattern, a channel layer covering an upper surface and side surfaces of the lower metal layer in the contact area and covering the upper surface and the side surfaces of the fin-type insulating pattern in the gate area, a gate pattern disposed over the channel layer in the gate area and extending in a second direction, and a source/drain contact pattern disposed over the channel layer in the contact area. The lower metal layer includes a Ti-based metal. The channel layer includes an oxide semiconductor material.