Multi-pass Memory Programming Sequence for Tighter Threshold Voltage Distributions
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Solution Overview
Problem
Current semiconductor memory programming techniques face challenges in achieving tight threshold voltage distributions without causing program disturb or neighboring word line interference, especially when programming multiple word lines to multi-level cell (MLC) states prior to fine programming passes.
Innovation Solution
The method involves dynamically determining the optimal number of word lines to be programmed to MLC before initiating the fine programming pass, alternating between MLC and fine passes to ensure that no more than the optimum number of word lines are programmed to MLC at a time, thereby minimizing program disturb and neighboring word line interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple word lines are programmed to MLC states before fine programming passes, then programming throughput is improved, but threshold voltage distribution becomes wider and program disturb increases
Solution Approach 1:
The patent segments the programming operation into distinct passes (MLC pass and fine pass) with different objectives. The MLC pass programs multiple word lines quickly to coarse data states, while the fine pass subsequently refines the threshold voltage distribution for previously programmed word lines. This segmentation allows throughput optimization in the MLC pass without sacrificing final precision, as the fine pass corrects the distribution width.
Solution Approach 2:
The MLC pass performs preliminary programming of multiple word lines to coarse data states before the fine programming pass refines them. By pre-programming word lines to approximate target states, the system achieves high initial throughput, and the subsequent fine pass completes the precision requirement without re-programming all word lines from scratch.
2Speed
If multiple word lines are programmed to MLC states simultaneously, then programming speed is improved, but neighboring word line interference increases
Solution Approach 1:
The patent divides the programming process into phases where word lines are programmed in groups during the MLC pass, followed by refinement phases. This segmentation limits the number of word lines actively programmed to MLC states at any given time, reducing cumulative interference while maintaining overall speed through parallel processing of multiple groups.
Solution Approach 2:
The programming operation alternates between MLC passes that program multiple word lines and fine passes that refine previously programmed word lines. This periodic alternation allows interference from MLC programming to subside before fine programming begins, reducing the cumulative effect of neighboring word line interference while maintaining programming throughput.
3Productivity
If the number of word lines programmed to MLC is increased, then programming efficiency is improved, but data retention and reliability deteriorate
Solution Approach 1:
The patent segments word lines into groups that are programmed to MLC states in batches, with subsequent fine programming passes refining each group. This segmentation ensures that even as more word lines are programmed to MLC states to improve efficiency, each group receives adequate fine programming attention to maintain tight threshold voltage distributions and prevent reliability degradation.
Solution Approach 2:
The fine programming pass provides feedback-based refinement by sensing the threshold voltage distribution of previously programmed word lines and applying additional programming only where needed. This feedback mechanism ensures that word lines programmed to MLC states achieve the required precision and reliability, even as the total number of MLC-programmed word lines increases for efficiency.
Data Source
AI summary
A controller is configured to program the memory cells to a first set of data states in a first programming pass and to a greater second set of data states in a second programming pass. The controller performs the first programming pass on the first word line. The controller then repeats the process of programming a portion of another word line and then comparing an upper tail of an erased data state of the first word line to a critical voltage until the upper tail of the erased data state of the first word line exceeds the critical voltage by a threshold. In response to the upper tail of the erased data state exceeding the critical voltage by the threshold, the controller then alternates between the first and second programming passes until the first programming pass is completed on the remaining word lines of the memory block.