Multi-Pass Memory Programming to Reduce Retention Error

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Solution Overview

Problem

NAND flash memory cells experience retention errors due to instant threshold voltage shifts (IVS) that cause data instability, especially in multi-level cells, leading to reduced read margins and invalid data.

Innovation Solution

Implement a multi-pass programming scheme with additional programming pulses or reprogramming steps after initial verification, targeting memory cells meant for higher programming states to stabilize threshold voltages and reduce IVS effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single-pass programming scheme is used, then programming speed is improved, but retention error increases due to insufficient threshold voltage stabilization

Engineering Contradiction:
Improveprogramming speedVSAvoiddata stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The programming operation is divided into multiple passes (first program pass, second program pass, and intermediate program passes) where each pass performs partial programming and verification. This segmentation allows the threshold voltage to be stabilized through repeated programming cycles, reducing retention error while maintaining acceptable programming speed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary programming passes before the final programming operation. In the first program pass, memory cells are programmed to intermediate states and verified. Additional intermediate program passes are performed for cells that need further stabilization. Only after these preliminary actions is the final programming state achieved, ensuring threshold voltage stability before the operation completes.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If multiple programming passes are implemented, then retention error is reduced through better threshold voltage stabilization, but programming time increases

Engineering Contradiction:
Improvedata stabilityVSAvoidprogramming time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The programming scheme dynamically adjusts the number of passes based on the target programming state. For higher programming states (e.g., P3, P4, P5, P6), additional intermediate program passes are performed to stabilize threshold voltage. For lower states, fewer passes are required. This dynamic adaptation reduces unnecessary programming time while ensuring reliability where needed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Different programming strategies are applied to different memory cells based on their target states. Memory cells targeting higher programming states receive additional intermediate program passes, while cells targeting lower states follow the standard two-pass scheme. This localized quality control optimizes the balance between reliability and time across the entire memory array.

Inventive Principle:
Principle #3Local quality

3Reliability

If additional intermediate program passes are performed for higher programming states, then threshold voltage stability is improved, but device complexity increases

Engineering Contradiction:
Improvethreshold voltage stabilityVSAvoidprogramming control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements verification steps after each program pass to check whether memory cells have reached their target threshold voltage. Based on the verification results, the control circuit determines whether additional intermediate program passes are needed. This feedback mechanism automates the complexity management, allowing the system to adaptively choose the minimum necessary passes without manual intervention.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12462886B2Method for programming a memory device to reduce retention error
Publication Date: 2025.11.04 YANGTZE MEMORY TECH CO LTD
  • US12462886B2 patent drawing
  • US12462886B2 patent drawing
  • US12462886B2 patent drawing

AI summary

In certain aspects, a memory device includes a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The plurality of memory cells includes a first set of memory cells configured to be programmed into a first set of programming states each of which is not lower than a first predetermined programming state. The control circuit is configured to perform a first program pass on the first set of memory cells. The control circuit is configured to continue to program at least a first memory cell from the first set of memory cells with one or more first programming voltages. A threshold voltage of the first memory cell is greater than a first verification voltage that corresponds to a first programming state of the first memory cell. The control circuit is configured to perform a second program pass on the first set of memory cells.