Multi-Pass Memory Programming Without First-Pass Verify Tests

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Solution Overview

Problem

Existing memory devices face challenges with neighbor word line interference (NWI) and data retention loss due to multi-pass programming, particularly as devices are scaled down, leading to upshifted and widened threshold voltage distributions and charge loss.

Innovation Solution

A multi-pass programming method is implemented without verify tests in the first program pass, using different bit line voltages to program memory cells to intermediate threshold voltage distributions, reducing the threshold voltage increase between passes and minimizing NWI and data retention loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If multi-pass programming is performed with verify tests in each pass, then programming accuracy is improved, but programming time and complexity increase

Engineering Contradiction:
Improveprogramming accuracyVSAvoidprogramming time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The programming process is divided into two distinct passes: a first pass without verify tests for rapid initial programming, and a second pass with verify tests for precision correction. This segmentation allows each pass to optimize for its specific function, reducing overall programming time while maintaining accuracy

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first pass performs preliminary programming action to establish initial threshold voltage distributions before the second pass refines them with verify tests. This preliminary action reduces the workload and time required in the subsequent precision pass

Inventive Principle:
Principle #10Preliminary action

2Object-affected harmful factors

If multi-pass programming is performed, then neighbor word line interference is reduced, but threshold voltage distribution shifts and widens

Engineering Contradiction:
Improveneighbor word line interferenceVSAvoidthreshold voltage distribution
Core Design Contradiction:
Object-affected harmful factorsVSManufacturing precision

Solution Approach 1:

The patent applies dynamic voltage adjustments between passes, using different bit line voltages in the first pass versus the second pass. This dynamic approach allows the system to adapt to the changing state of memory cells after initial programming, correcting threshold voltage shifts caused by neighbor word line interference

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The second pass uses verify tests to detect threshold voltage distribution shifts caused by neighbor word line interference, then applies corrective programming based on this feedback to restore accurate voltage distributions

Inventive Principle:
Principle #23Feedback

3Reliability

If verify tests are performed in every program pass, then programming reliability is improved, but device complexity and operation difficulty increase

Engineering Contradiction:
Improveprogramming reliabilityVSAvoidoperation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Verify tests are segmented to only the second pass rather than being applied uniformly to all passes. This reduces operational complexity while maintaining reliability through strategic verification at the critical refinement stage

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies verify tests partially - only in the second pass where they provide maximum benefit for correcting threshold voltage distributions. This partial application reduces complexity while maintaining sufficient reliability for the programming operation

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentEP3711053B1Multi-pass programming process for memory device which omits verify test in first program pass
Publication Date: 2025.08.20 SANDISK TECHNOLOGIES LLC
  • EP3711053B1 patent drawingFigure 1
  • EP3711053B1 patent drawingFigure 2
  • EP3711053B1 patent drawingFigure 3

AI summary

Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.