Multi-pass Programming for Tight Vt Distribution in Flash Memory
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Solution Overview
Problem
Conventional flash memory devices face challenges in achieving tight threshold voltage (Vt) distributions and minimizing program disturb without compromising programming speed, as smaller programming voltage steps improve distribution tightness but increase time, and floating gate-to-floating gate capacitive coupling and program disturb widen distributions.
Innovation Solution
A multi-pass programming method is employed, where the first pass uses larger voltage increments to quickly program lower levels and the uppermost level, followed by a second pass with smaller increments to fine-tune lower levels, reducing floating gate-to-floating gate coupling and program disturb, while maintaining programming speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If smaller programming voltage steps are used, then Vt distribution tightness is improved, but programming time increases
Solution Approach 1:
The programming operation is divided into multiple passes, where different voltage step sizes are applied in different passes. The first pass uses larger voltage steps for coarse programming, while subsequent passes use smaller voltage steps for fine-tuning, thereby achieving tight Vt distributions without excessive programming time
Solution Approach 2:
The voltage step size is made dynamic rather than static. The programming method adapts the voltage step size based on the programming stage: larger steps initially for speed, then smaller steps later for precision, optimizing both time and distribution tightness
2Productivity
If larger programming voltage steps are used, then programming speed is improved, but Vt distribution tightness deteriorates
Solution Approach 1:
The programming process is segmented into multiple passes with different voltage step characteristics. Early passes use larger voltage steps to achieve fast programming speed, while later passes use smaller voltage steps to tighten the Vt distribution, thus balancing speed and precision
3Quantity of substance
If memory cell density is increased, then storage capacity is improved, but floating gate-to-floating gate capacitive coupling increases
Solution Approach 1:
The programming method applies preliminary programming pulses with carefully controlled voltage steps before the effects of capacitive coupling become significant. By programming cells in a specific sequence and with appropriate voltage step sizes, the method compensates for and reduces the harmful effects of capacitive coupling between adjacent floating gates
4Adaptability or versatility
If programming voltage is increased to program higher states, then multilevel cell programming is achieved, but program disturb occurs
Solution Approach 1:
Different voltage step sizes and programming conditions are applied to different target states. Lower states are programmed with smaller voltage steps to avoid disturb, while the uppermost state is programmed with larger voltage steps for efficiency. This localized optimization of programming parameters reduces program disturb while maintaining multilevel cell capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in narrower Vt distributions and reduced program disturb without impacting programming throughput, allowing for efficient storage of multiple bits per cell without significant increases in programming time.
Implementation Method 1
Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The charge can be removed from the floating gate by a block erase operation.
Implementation Method 2
Each cell's threshold voltage (Vt) determines the data that is stored in the cell. The multilevel cell may have multiple Vt ranges that each indicates a different state.
Implementation Method 3
Between each program pulse, a verify 203 is performed to determine if the cell's target Vt has been achieved.
Data Source
AI summary
A method for programming a memory device, a memory device, and a memory system are provided. According to at least one such method, a first programming pass generates a plurality of first programming pulses to increase the threshold voltages of target memory cells to either a pre-program level or to the highest programmed threshold. A second programming pass applies a plurality of second programming pulses to the target memory cells to increase their threshold voltages only if they were programmed to the pre-program level. The target memory cells programmed to their respective target threshold levels during the first pass are not programmed further.