Multi-pass Programming for Non-volatile Memory Coupling
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Solution Overview
Problem
In non-volatile semiconductor memory devices, such as EEPROM and flash memory, the coupling between adjacent floating gates leads to shifts in the apparent charge stored, causing erroneous readings, especially in multi-state devices where the allowed threshold voltage ranges are narrower, and this effect worsens as memory cells shrink in size due to short channel effects and increased coupling ratios.
Innovation Solution
A multi-pass programming technique is employed where a non-volatile storage element is programmed to a first verify level, read to confirm this level is reached, and then further programmed to a second verify level, with read operations and error correction processes used to adjust programming passes across word lines to minimize coupling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-state flash memory devices are used to increase storage capacity, then the amount of data that can be stored is improved, but the floating gate to floating gate coupling shifts memory cells from allowed threshold voltage ranges to forbidden ranges causing erroneous readings
Solution Approach 1:
The patent segments the programming process into multiple passes (coarse programming followed by fine programming) and divides the memory array into different word line groups that are programmed sequentially. This segmentation allows threshold voltage distributions to be tightened in stages, preventing coupling-induced shifts from causing erroneous readings while maintaining multi-state storage capacity.
Solution Approach 2:
The patent performs preliminary coarse programming of memory cells to establish initial threshold voltage levels before subsequent fine programming. This preliminary action creates a foundation that reduces the impact of floating gate coupling, ensuring that memory cells remain within allowed threshold voltage ranges throughout the programming process.
2Area of stationary object
If memory cells are shrunk to increase device density, then the amount of memory that can be packed is improved, but the coupling between adjacent floating gates increases causing threshold voltage shifts
Solution Approach 1:
The patent segments the memory array into different word line groups that are programmed in a specific sequence. By programming alternate word lines first and then returning to program remaining lines, the patent reduces simultaneous coupling effects between adjacent floating gates, enabling higher device density without excessive threshold voltage shifts.
Solution Approach 2:
The patent employs periodic programming sequences where word lines are programmed in alternating patterns (e.g., even word lines first, then odd word lines). This periodic action allows coupling effects to be distributed and managed over time, preventing cumulative threshold voltage shifts that would occur with continuous sequential programming of all word lines.
3Productivity
If programming voltage is applied to raise threshold voltage quickly, then programming speed is improved, but threshold voltage distribution becomes wider causing coupling effects to shift cells to forbidden ranges
Solution Approach 1:
The patent segments the programming operation into coarse programming and fine programming passes. The coarse pass applies higher programming voltages to quickly raise threshold voltages toward target levels, while the fine pass applies lower voltages to precisely tighten the threshold voltage distribution. This segmentation achieves both high programming speed and narrow threshold voltage distributions.
Solution Approach 2:
The patent performs coarse programming that intentionally raises threshold voltages slightly above target levels, then uses fine programming to precisely adjust and tighten the distribution. This partial or excessive initial action allows for faster overall programming while ensuring final precision through the corrective fine programming pass.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the impact of floating gate to floating gate coupling, enhancing the accuracy of data storage and retrieval in multi-state devices by tightening threshold voltage distributions and reducing hardware requirements and costs.
Implementation Method 1
When programming an EEPROM or flash memory device, such as a NAND flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate.
Implementation Method 2
The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate.
Implementation Method 3
Shifts in the apparent charge stored on a floating gate can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates.
Data Source
AI summary
Coupling effects between adjacent floating gates in a non-volatile storage device are reduced in a multi-pass programming operation, while reducing program data storage requirements. In one approach, storage elements are programmed in an out of sequence or zigzag word line order. A particular word line is programmed with a coarse program pass, after which another word line is programmed with a fine program pass, after which the particular word line is read. The particular word line is read before another word line is programmed with a coarse program pass which causes coupling interference to storage elements of the particular word line. The read data is subsequently used to perform a fine program pass for the particular word line. This avoids the need to store program data of multiple word lines concurrently, so that storage hardware can be reduced in size along with power consumption.