Multi-Path ESD Clamp Circuit for Lower Overshoot and Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges with voltage overshoot during electrostatic discharge (ESD) events, particularly with diode string triggered SCRs (DTSCRs) and low voltage triggered SCRs (LVTSCRs, due to capacitance factors, which affect the performance and reliability of ESD protection.
Innovation Solution
The semiconductor device incorporates a configuration with diodes and power clamp circuits, including multiple parallel diodes and SCR circuits, strategically arranged to manage ESD currents and reduce voltage drop, enhancing ESD robustness and lowering parasitic capacitance for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DTSCR is used for ESD protection, then ESD protection capability is improved, but voltage overshoot occurs during ESD events
Solution Approach 1:
The patent divides the ESD protection function into multiple parallel paths: a first ESD path through a first SCR and a second ESD path through a second SCR. This segmentation allows the ESD current to be distributed across multiple devices, reducing the voltage overshoot experienced by any single device while maintaining overall ESD protection capability.
2Speed
If LVTSCR is used for ESD protection, then triggering speed is improved, but capacitance increases affecting performance
Solution Approach 1:
The patent segments the ESD protection function across multiple parallel SCR devices, allowing the use of LVTSCR structures that provide fast triggering. By distributing the function across multiple devices rather than relying on a single high-capacitance device, the overall capacitance impact is reduced while maintaining fast triggering performance.
Solution Approach 2:
The patent employs multiple SCRs in parallel where the combined ESD protection capability exceeds what a single device would provide. This partial action approach allows each individual SCR to operate with lower capacitance requirements while the collective system provides robust ESD protection with fast triggering response.
3Device complexity
If single ESD path is used, then device complexity is reduced, but ESD protection robustness is insufficient
Solution Approach 1:
The patent implements multiple ESD paths with separate SCR devices, each capable of independently conducting ESD current. This segmentation enhances ESD protection robustness by providing redundant protection paths, ensuring that if one path is compromised, other paths remain available to protect the circuit.
Solution Approach 2:
The patent utilizes SCRs with different breakdown voltages and characteristics in parallel configurations. By changing the parameters of individual SCR devices (such as triggering voltage and current characteristics), the system achieves enhanced ESD robustness while managing overall device complexity through parameter optimization rather than uniform device selection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively discharges ESD currents with reduced voltage drop across internal circuits, enhancing the robustness of integrated circuit devices and supporting high-speed applications by utilizing bidirectional SCR circuits and optimized diode arrangements.
Implementation Method 1
The semiconductor device includes a first electrostatic discharge (ESD) path configured to conduct a first ESD current and a second ESD path configured to conduct a second ESD current
Data Source
AI summary
A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.