Multi-Path ESD Protection Circuit for Low-Overshoot I/O Pads
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Solution Overview
Problem
Existing semiconductor devices face challenges with voltage overshoot during electrostatic discharge (ESD) events, particularly with diode string triggered SCRs (DTSCRs) and low voltage triggered SCRs (LVTSCRs, due to capacitance factors, which affect the performance and reliability of ESD protection.
Innovation Solution
The semiconductor device incorporates a configuration with multiple diodes and power clamp circuits, forming equivalent silicon controlled rectifier (SCR) circuits to effectively discharge ESD current, reducing voltage drop and enhancing ESD robustness by utilizing diodes and parasitic transistors to direct ESD current between input/output (I/O) pads and voltage terminals, thereby improving capacitance management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DTSCR is used for ESD protection, then ESD robustness is improved, but voltage overshoot occurs during ESD events
Solution Approach 1:
The patent divides the ESD protection function into multiple independent DTSCR units arranged in parallel. Each DTSCR unit independently handles a portion of the ESD current, distributing the stress and preventing excessive voltage overshoot that would occur in a single-unit configuration. This segmentation allows the system to maintain robust ESD protection while controlling voltage spikes.
2Object-affected harmful factors
If LVTSCR is used for ESD protection, then voltage control is improved, but capacitance performance requires enhancement
Solution Approach 1:
The patent combines multiple LVTSCR units in parallel to achieve both voltage control and improved capacitance performance. By merging multiple units, the total effective capacitance increases while each unit continues to provide voltage control functionality. This combination allows the system to overcome the capacitance limitation of individual LVTSCR units.
3Reliability
If multiple diodes and power clamp circuits are used to form equivalent SCR circuits, then ESD robustness is enhanced, but device complexity increases
Solution Approach 1:
The patent designs each diode and power clamp circuit combination to serve multiple functions: ESD current diversion, voltage clamping, and capacitance management. By making these components multi-functional, the system achieves enhanced ESD robustness without proportionally increasing complexity, as each component performs several protective roles simultaneously rather than requiring separate dedicated components for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces voltage drop across internal circuits during ESD events, enhancing the robustness of ESD protection and lowering parasitic capacitance, making it suitable for high-speed applications.
Implementation Method 1
An ESD event produces extremely high voltages and leads to pulses of high current of a short duration that can damage integrated circuit devices
Implementation Method 2
LVTSCRs have performance required to improve because of capacitance factor
Data Source
AI summary
A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.