Multi-Path OTA Architecture for Higher Transconductance and Gain

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Solution Overview

Problem

Conventional operational transconductance amplifiers (OTAs) face limitations in speed and noise due to insufficient transconductance, often requiring high power consumption to achieve increased transconductance, which results in lower direct-current gain and larger active load transistors.

Innovation Solution

The implementation of an OTA with three transconductance (Gm) paths, including a first pair of input transistors coupled with cascode transistors, a second pair of input transistors coupled with cascode transistors, and a third pair of input transistors connected to the second pair of cascode transistors, enhancing transconductance while reducing active load transistor size and increasing output impedance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If conventional OTA uses high power consumption to achieve increased transconductance, then transconductance is improved, but direct-current gain deteriorates and active load transistor size increases

Engineering Contradiction:
ImprovetransconductanceVSAvoidactive load transistor size
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The patent divides the single transconductance path into three separate Gm paths (first Gm path with first pair of input transistors and first pair of cascode transistors, second Gm path with second pair of input transistors and second pair of cascode transistors, and third Gm path with third pair of input transistors), allowing each path to contribute independently to the total transconductance without requiring oversized active load transistors

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extends the conventional single-path architecture into a multi-dimensional structure by adding multiple parallel Gm paths with different transistor pairs and cascode configurations, enabling transconductance enhancement through structural dimensionality rather than simply increasing power consumption or transistor size

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Power

If conventional OTA increases transconductance through high power consumption, then transconductance is improved, but speed and noise performance deteriorate

Engineering Contradiction:
ImprovetransconductanceVSAvoidspeed and noise performance
Core Design Contradiction:
PowerVSSpeed

Solution Approach 1:

By segmenting the transconductance function into three separate Gm paths with dedicated input transistor pairs and cascode transistor pairs, each path can be optimized for speed and noise performance independently, with the third Gm path specifically contributing to enhanced speed and reduced noise without the negative effects of high power consumption in a single path

Inventive Principle:
Principle #1Segmentation

3Power

If conventional OTA uses larger active load transistors to achieve higher transconductance, then transconductance is improved, but output impedance decreases

Engineering Contradiction:
ImprovetransconductanceVSAvoidoutput impedance
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The patent segments the load function across multiple cascode transistor pairs (first pair of cascode transistors, second pair of cascode transistors) distributed across three Gm paths, allowing each cascode pair to maintain high output impedance while collectively providing the required transconductance without needing oversized individual transistors

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240429887A1Operational transconductance amplifier with boosted transconductance
Publication Date: 2024.12.26 QUALCOMM INC
  • US20240429887A1 patent drawing
  • US20240429887A1 patent drawing
  • US20240429887A1 patent drawing

AI summary

Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to an operational transconductance amplifier (OTA). One example amplifier generally includes: a first pair of input transistors; a first pair of cascode transistors coupled in cascode with the first pair of input transistors, respectively; a second pair of input transistors; a second pair of cascode transistors coupled in cascode with the second pair of input transistors, respectively; and a third pair of input transistors coupled to the second pair of cascode transistors, respectively.