Multi-Path Pattern Generator for Branch Handling in Automatic Test Systems
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Solution Overview
Problem
Automatic test equipment face challenges in generating and measuring test signals at high rates required for modern semiconductor devices, particularly due to the complexity of executing test patterns with conditional branches, which can lead to stalled pipelines and incorrect test results.
Innovation Solution
The implementation of a pattern generator with multiple processing paths that allow for sequential execution from different locations within the test pattern, using pipelined circuitry to process operation portions and determine branch destinations, enabling same-cycle branching and reducing the risk of pipeline stalls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional single-path pipeline architecture is used to execute test patterns, then the device complexity is reduced, but the processing speed decreases due to pipeline stalls caused by conditional branches
Solution Approach 1:
The pattern generator is divided into multiple independent processing paths (first path, second path, third path, etc.), each capable of independently executing test pattern vectors. This segmentation allows simultaneous processing of multiple vector sequences, enabling the system to maintain high-speed operation even when conditional branches occur in one path, as other paths continue processing without interruption.
Solution Approach 2:
The invention transitions from a single-dimensional sequential processing approach to a multi-dimensional parallel processing architecture. By adding the dimension of multiple concurrent processing paths, the system can execute test patterns in parallel, effectively increasing the overall processing speed without being constrained by single-path pipeline stalls.
2Measurement precision
If the tester performs multiple operations to generate or measure test signals for each DUT cycle, then the measurement precision is improved, but the productivity decreases due to inability to keep up with high-speed DUT operation
Solution Approach 1:
Multiple processing paths are prepared in advance, each pre-configured to handle specific portions of test pattern execution. When a conditional branch occurs in the active path, the system can immediately switch to or initiate processing in another pre-prepared path, eliminating the need to wait for the current path to complete all operations. This preliminary preparation of multiple execution paths enables the tester to maintain high productivity while performing multiple measurement operations.
3Productivity
If a pipelined architecture is used to execute test patterns, then the processing speed is improved, but the reliability decreases due to pipeline stalls when conditional branches are encountered
Solution Approach 1:
The multiple processing paths act as intermediaries that can take over when the primary execution path encounters a conditional branch. Instead of stalling the entire pipeline, the system uses alternative paths as mediators to continue test pattern execution, ensuring that test signal generation and measurement operations proceed without interruption, thereby maintaining both high productivity and reliable test results.
Data Source
AI summary
According to some aspects, a method of operating an automatic test system comprising a plurality of paths and programmed with a test pattern is provided. One such method comprises executing vectors in the test pattern with circuitry comprising a plurality of paths, the executing comprising upon processing, in a first of the plurality of paths, the operation portion of a vector specifying an operation capable of generating a branch in the flow of execution of the vectors in the test pattern to a non-sequential location in the test pattern, initiating processing of the test pattern in a second of the plurality of paths from the non-sequential location. Some aspects include a system for executing instructions comprising a plurality of paths comprising control circuitry to initiate processing of operation portions from sequential locations of a memory within an available path of the plurality of paths.