Multi-Path Via Structure for IC Packaging Density

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Solution Overview

Problem

Current semiconductor technology requires multiple vias with single electrical paths, leading to increased complexity and reduced miniaturization potential due to the need for multiple vias to connect multiple electrical paths between layers in integrated circuit packaging substrates.

Innovation Solution

The development of vias with multiple electrical paths, where each path is isolated by an insulator, allowing for compact packaging by reducing the number of individual vias needed, achieved through methods such as drilling, conductive material deposition, and photoresist patterning to create multiple conductive pathways within a single via.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple vias with single electrical paths are used, then electrical connectivity between layers is achieved, but device complexity increases and miniaturization potential is reduced

Engineering Contradiction:

Improveelectrical connectivityVSAvoidvia structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple single-path vias into a single via structure containing multiple electrical paths. The via includes a body with multiple conductive paths extending between first and second surfaces, allowing multiple electrical connections to be achieved through one unified structure rather than multiple separate vias, thereby reducing device complexity while maintaining connectivity

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The via structure is designed to perform multiple functions simultaneously - it provides multiple electrical paths between layers, acts as an interconnect structure, and can be formed through a unified manufacturing process. The single via body serves universal purposes that previously required multiple specialized vias

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If multiple vias are used to connect multiple electrical paths, then electrical connectivity is achieved, but packaging compactness is reduced

Engineering Contradiction:

Improveelectrical connectivityVSAvoidpackaging area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

Multiple vias are merged into a single via body that contains multiple electrical paths. This consolidation reduces the total area occupied by via structures, as one multi-path via replaces what would have been multiple separate vias, each requiring their own opening and conductive filling

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Multiple electrical paths are nested within a single via body structure. The conductive paths are arranged in close proximity within the via, allowing them to occupy shared space rather than requiring separate spatial locations, thereby reducing the overall packaging area

Inventive Principle:

Principle #7Nested doll (Nesting)

3Reliability

If multiple vias are used for multiple electrical paths, then circuit connectivity is achieved, but miniaturization capability is reduced

Engineering Contradiction:

Improvecircuit connectivityVSAvoidfeature size

Core Design Contradiction:

ReliabilityVSLength of moving object

Solution Approach 1:

The patent combines multiple electrical paths into a single via structure, reducing the number of discrete features that need to be formed. This merging allows for smaller overall feature sizes since the multi-path via occupies less space than multiple individual vias, enabling better miniaturization of circuit features

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables more compact and efficient packaging by allowing multiple electrical paths within a single via, reducing the number of vias required and balancing circuit density and spacing constraints, thereby enhancing miniaturization capabilities.

Implementation Method 1

lining the opening with a conductive material

Methodology Applied

Scientific EffectElectroplating: Electroplating

Implementation Method 2

lining the opening with a conductive material

Methodology Applied

Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Implementation Method 3

placing a photoresist material over the via opening and exposing the photoresist material to light

Methodology Applied

Scientific EffectPhotopolymerization: Photopolymerisation

Implementation Method 4

removing a portion of the photoresist material to form a patterned photoresist

Methodology Applied

Scientific EffectChemical etching:

Data Source

PatentUS7952202B2Method of embedding passive component within via

Publication Date: 2011.05.31 TAHOE RES LTD

AI summary

A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.