Multi-patterning Layout Conflict Detection via Graph Odd Loops
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Solution Overview
Problem
Current semiconductor fabrication methods, such as double patterning, face challenges in reducing line spacing below 45 nanometers due to resolution blurring and native conflicts, which limit design freedom and efficiency in multi-patterning processes.
Innovation Solution
A method is introduced to pre-group patterns on a metal layer, allowing assignment to the same photomask while checking for conflicts using a reduced graph approach that identifies odd loops, enabling quick identification and modification of layouts to eliminate conflicts, thereby facilitating conflict-free double patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double patterning is used to reduce line spacing below 45nm, then manufacturing precision is improved, but device complexity increases due to multiple masks and processing steps
Solution Approach 1:
The patent applies preliminary action by performing conflict detection and pre-grouping of patterns before the actual multi-patterning fabrication process. The system analyzes the layout, identifies potential conflicts using graph theory, and pre-assigns patterns to masks, thereby resolving conflicts in advance and simplifying the subsequent fabrication process.
Solution Approach 2:
The patent introduces an intermediary computational layer between design and fabrication. A conflict detection system using graph theory acts as a mediator that analyzes pattern relationships, identifies odd loops and conflicts, and generates pre-grouping assignments, thereby bridging the gap between layout design and multi-patterning manufacturing.
2Manufacturing precision
If layout modifications are made to resolve native conflicts, then manufacturing precision is improved, but productivity decreases due to extended design iteration
Solution Approach 1:
The patent implements feedback by creating a closed-loop system that automatically detects conflicts in the layout, provides information about odd loops and conflicting patterns, and enables pre-grouping assignments. This feedback mechanism allows designers to resolve conflicts systematically without extensive manual iteration, improving both precision and productivity.
Solution Approach 2:
The system enables self-service by automatically performing conflict detection and analysis without requiring manual intervention. The graph-based conflict detection system autonomously identifies issues and provides pre-grouping recommendations, reducing the need for repeated manual layout modifications and accelerating the design flow.
3Ease of manufacture
If existing lithographic tools are used for multi-patterning, then cost is reduced, but manufacturing precision deteriorates due to resolution blurring at small dimensions
Solution Approach 1:
The patent applies segmentation by dividing the pattern formation process into multiple discrete steps using multiple masks. Instead of attempting to form all patterns in a single exposure, the system segments the patterns into different groups that can be formed sequentially on different masks, thereby achieving sub-45nm resolution using existing lithographic tools with larger numerical apertures.
Data Source
AI summary
A method comprises (a) receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool, the layout including a plurality of polygons to be formed in the DPT-layer by a multi-patterning process; (b) receiving at least one identification of a subset of the plurality of polygons that are to be formed in the DPT-layer using the same photomask as each other; (c) constructing a graph of the subset of the plurality of polygons and any intervening polygons of the plurality of polygons, where the subset of the plurality of polygons are represented in the graph by a single node, the graph including connections connecting adjacent ones of the polygons in the graph that are positioned within a threshold distance of each other; and (d) identifying a multi-patterning conflict if any subset of the connections form an odd loop.