Multi-Patterning Overlay Error Measurement via Computational Alignment
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Solution Overview
Problem
Current methods for determining overlay error between patterned features in multi-patterning steps of semiconductor fabrication are limited in accuracy and cannot effectively measure overlay errors on complex patterns, often relying on special targets and symmetry-based approaches that fail to predict actual in-die errors.
Innovation Solution
A system and method using an energy source and detector to align and shift patterned features on a wafer, determining relative overlay error by comparing design and image-based center lines, enabling precise alignment and measurement of overlay errors without relying on special targets or symmetry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If symmetry-based approaches and special targets are used for overlay measurement, then measurement can be performed with existing methods, but measurement precision deteriorates for complex patterns and in-die errors cannot be accurately predicted
Solution Approach 1:
The patent segments the overlay measurement process into distinct computational steps: obtaining design data for multiple patterning steps, obtaining measured wafer data, aligning the design data to the measured data, shifting specific patterning step data, and determining offsets. This segmentation allows each step to be optimized independently, enabling high-precision measurement of complex in-die patterns without relying on symmetry-based special targets.
Solution Approach 2:
The patent replaces physical mechanical alignment systems with computational alignment methods. Instead of using special symmetry-based targets and mechanical alignment tools, the system uses computer-subsystem-based image processing and data alignment algorithms to achieve precise overlay measurement, thereby improving both precision and adaptability to complex patterns.
2Manufacturing precision
If conventional overlay measurement methods are used, then existing equipment can be utilized, but manufacturing precision deteriorates due to inability to measure small-scale errors
Solution Approach 1:
The patent extends the measurement capability from traditional special target locations to the entire in-die area by utilizing comprehensive design data and measured wafer data. The computational alignment process analyzes patterns across multiple dimensions and locations, enabling detection of small-scale overlay errors (2-5 nm) throughout the die rather than at isolated measurement points.
Solution Approach 2:
The patent creates a computational model by copying and aligning design data with measured wafer data. The design data serves as a reference model that is computationally aligned to the actual measured patterns, allowing precise determination of overlay errors by comparing the ideal design positions with actual measured positions across the entire die.
3Productivity
If manual or semi-automated alignment processes are used, then existing systems can be implemented, but productivity deteriorates due to time-consuming measurements
Solution Approach 1:
The patent implements a self-service automated system where the computer subsystem automatically obtains design data, obtains measured wafer data, performs alignment, executes the shifting operation, and calculates overlay offsets without manual intervention. This automation eliminates time-consuming manual processes and enables high-throughput overlay measurement, significantly improving productivity while maintaining high precision.
Data Source
AI summary
Methods and systems for determining overlay error between different patterned features of a design printed on a wafer in a multi-patterning step process are provided. For multi-patterning step designs, the design for a first patterning step is used as a reference and designs for each of the remaining patterning steps are synthetically shifted until the synthetically shifted designs have the best global alignment with the entire image based on global image-to-design alignment. The final synthetic shift of each design for each patterning step relative to the design for the first patterning step provides a measurement of relative overlay error between any two features printed on the wafer using multi-patterning technology.