Multi-patterning Vias with High-Carbon Dielectric Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The optical proximity effect poses a challenge in transferring patterns from lithography masks to wafers, particularly when features are closely located, leading to distorted or shortened features due to increased down-scaling in integrated circuit manufacturing.
Innovation Solution
A multiple patterning method involving the use of high-carbon dielectric layers and capping layers to maintain etching selectivity and pattern accuracy, utilizing a series of etching and ashing processes to form vias with straight profiles and uniform dimensions, thereby reducing the optical proximity effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double-patterning technology is used to increase feature density, then optical proximity effect is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent divides the patterning process into multiple discrete steps (first lithography exposure, first etching, second lithography exposure, second etching) to form different via types. This segmentation allows each step to be optimized independently, reducing optical proximity effects while maintaining manageable process complexity through systematic breakdown of the overall fabrication sequence.
Solution Approach 2:
The patent employs periodic alternating actions of lithography exposure and etching processes. By cycling through exposure-etching sequences with different mask patterns, the method achieves high feature density and straight via profiles through repeated application of controlled patterning and material removal steps.
2Shape
If multiple etching processes are used to form different via types, then via profile straightness is improved, but process time increases
Solution Approach 1:
The etching process is segmented into multiple specialized etching steps, each targeting specific via types (first type vias, second type vias, third type vias). This segmentation enables precise control of via profiles and dimensions, achieving straight via walls through dedicated etching conditions for each via category.
Solution Approach 2:
The patent changes etching parameters (etchant composition, temperature, pressure, power) between different etching steps to optimize via profile formation. By adjusting these parameters for each etching process, the method achieves straight via profiles and uniform dimensions while managing overall process time through efficient parameter optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures high etching selectivity and uniformity in via openings, maintaining vertical sidewalls and consistent lateral dimensions, improving the accuracy and density of feature transfer in integrated circuit manufacturing.
Implementation Method 1
forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer... maintain etching selectivity
Implementation Method 2
utilizing a series of etching and ashing processes to form vias with straight profiles
Data Source
AI summary
A method includes forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer, forming a capping layer over the carbon-containing layer, forming a first photo resist over the capping layer, and etching the capping layer and the carbon-containing layer using the first photo resist as a first etching mask. The first photo resist is then removed. A second photo resist is formed over the capping layer. The capping layer and the carbon-containing layer are etched using the second photo resist as a second etching mask. The second photo resist is removed. A third photo resist under the carbon-containing layer is etched using the carbon-containing layer as etching mask. A dielectric layer underlying the third photo resist is etched to form via openings using the third photo resist as etching mask. The via openings are filled with a conductive material.