Multi-Phase Clock Phase Adjustment Circuit for Timing Skew
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Solution Overview
Problem
Conventional data transmission systems face challenges in high-speed data transfer due to signal delay differences caused by varying wiring lengths between master and slave devices, which affect the phase shifting of timing signals, hindering efficient data conversion between serial and parallel data.
Innovation Solution
A semiconductor device with internal clock generating circuits that produce multi-phase clock signals and phase adjusting circuits to correct timing skew, ensuring uniform data window widths and valid times for input and output operations, thereby improving the device's characteristics by synchronizing data transfer with multi-phase clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer speed is increased to achieve high-speed communication, then productivity is improved, but signal delay differences due to wiring length variations cause timing skew that deteriorates reliability
Solution Approach 1:
The patent segments the timing control function by providing separate timing adjustment circuits for each data line. Each timing adjustment circuit independently adjusts the phase of timing signals for its corresponding data line, allowing precise compensation for wiring length differences without affecting other data lines. This segmentation enables high-speed data transfer while maintaining reliable timing synchronization across all lines.
Solution Approach 2:
The patent applies local quality by making each timing adjustment circuit customizable for its specific data line. The adjustment amount and direction (advance or delay) can be individually set for each line based on its specific wiring characteristics. This localized adjustment ensures that each data line receives the precise timing correction it needs, maintaining overall system reliability at high transfer speeds.
2Adaptability or versatility
If multiple timing signals with different phases are supplied to input and output circuits, then data conversion between serial and parallel is enabled, but wiring length differences cause signal delay variations that deteriorate manufacturing precision
Solution Approach 1:
The patent implements preliminary action by pre-adjusting the phase of timing signals before they reach the input and output circuits. The timing adjustment circuits compensate for known wiring length differences in advance, ensuring that all timing signals arrive at their destination with the correct phase relationship. This preliminary correction enables accurate data conversion while accounting for manufacturing variations in wiring lengths.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the phase parameter of timing signals to compensate for wiring variations. Each timing adjustment circuit modifies the phase parameter of its corresponding timing signal based on the specific wiring characteristics, maintaining accurate phase relationships despite manufacturing tolerances in wiring lengths.
3Reliability
If phase of clock signal is preliminarily adjusted at master device side, then signal delay difference is absorbed, but internal processing speed cannot catch up with increasing data transfer speed
Solution Approach 1:
The patent applies dynamics by making the timing adjustment configurable and adaptable. The timing adjustment circuits can be programmed with different adjustment amounts based on the specific application requirements and wiring characteristics. This dynamic adjustment capability allows the system to optimize both timing synchronization and processing speed according to the actual operating conditions, rather than being fixed at design stage.
Data Source
AI summary
To provide a semiconductor device including a data input circuit and a data output circuit connected to a plurality of data input/output terminals, where at least one of the data input circuit and the data output circuit fetches data in response to multi-phase clock signals having different phases to be timing signals for fetching data, and adjusts a valid range for fetching data to be substantially uniform for each of the multi-phase clock signals. According to the present invention, the window width of data can be made uniform by individually adjusting the multi-phase clock signals that are input or output timing signals, and thus characteristics of the semiconductor device can be improved.