Multi-Phase Clock Divider Stages Without PLL or DLL Complexity

Solution Overview

Problem

Existing multiple-phase clock generators using phase-locked loops (PLL) or delay-locked loops (DLL) are large in size and complex, making them expensive and difficult to implement in integrated circuits.

Innovation Solution

A multiple-phase clock generator design utilizing flip-flops and inverters to create multiple stages of dividers, where each stage divides the clock frequency by 2, generating equally distributed multiple-phase clock signals with a consistent phase difference, simplifying the implementation compared to traditional PLL or DLL circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a phase-locked loop (PLL) or delay-locked loop (DLL) is used to generate multiple-phase clocks, then the clock signals can be generated with proper phase relationships, but the circuit size becomes large and the implementation becomes complicated and expensive

Engineering Contradiction:

Improveclock signal generationVSAvoidcircuit implementation

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The circuit is divided into multiple identical stages, where each stage contains a divider and an inverter. Each stage processes the clock signal independently to generate phase-shifted outputs, avoiding the need for complex interconnected PLL/DLL components while maintaining proper phase relationships through modular repetition

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent uses multiple copies of the same simple divider-inverter stage to generate multiple-phase clocks. Instead of implementing a complex single-stage PLL or DLL, several identical simplified stages are replicated and connected in sequence, each producing a phase-shifted version of the input clock signal

Inventive Principle:

Principle #26Copying

2Reliability

If a phase-locked loop (PLL) or delay-locked loop (DLL) is used to generate multiple-phase clocks, then the clock signals can be generated with proper phase relationships, but the circuit size becomes large

Engineering Contradiction:

Improveclock signal generationVSAvoidcircuit size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The circuit is divided into multiple identical stages, where each stage contains a divider and an inverter. Each stage processes the clock signal independently to generate phase-shifted outputs, avoiding the need for complex interconnected PLL/DLL components while maintaining proper phase relationships through modular repetition

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent replaces expensive, large-scale PLL or DLL implementations with multiple instances of simple, minimal circuit stages. Each stage uses basic divider and inverter components that occupy minimal silicon area, collectively providing the same functionality as a much larger traditional implementation

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS8884665B2Multiple-phase clock generator

Publication Date: 2014.11.11 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A multiple-phase clock generator includes at least one stage of dividers. A clock signal is supplied as a first stage clock input to dividers in a first stage of dividers. An N-th stage includes 2N dividers, where N is a positive integer number. Each divider in the first stage is configured to divide a first clock frequency of the first stage clock input by 2 to provide a first stage output. Each divider in the N-th stage is configured to divide an N-th clock frequency of an N-th stage clock input by 2 to provide an N-th stage output. The N-th stage outputs from the dividers in the N-th stage provide 2N-phase clock signals that are equally distributed with a same phase difference between adjacent phase clock signals.