Multi-Phase Clock Circuitry Using Loop Logic for Phase Accuracy
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Solution Overview
Problem
Existing multi-phase clock signal generators face challenges in generating a large number of clock signals with increasing phase delays, such as 8-phase signals, due to limitations in phase accuracy, robustness, and frequency range, particularly when using phase interpolator circuits and logic gates which can lead to phase swapping and reduced maximum frequency of operation.
Innovation Solution
A circuitry and method that utilizes a loop-connected arrangement of logic components, where each component receives three input signals and masks out the third input signal based on the first and second input signals, ensuring a fixed order of phase delays and robust generation of output clock signals, doubling the number of output clock signals compared to input signals, without the need for D-type flip-flop circuits or latches, thus supporting high frequencies and wide frequency ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If phase interpolator circuits are used to generate 8-phase clock signals, then the number of clock signals can be increased, but phase accuracy deteriorates and requires calibration to track temperature variations
Solution Approach 1:
The circuit divides the generation of 8-phase clock signals into two independent 4-phase clock signal generators. Each generator produces 4 clock signals with 90-degree phase shifts using D-type flip-flops. This segmentation allows each generator to operate independently with guaranteed phase accuracy, avoiding the calibration issues of phase interpolators while still achieving the desired 8-phase output when combined.
2Quantity of substance
If logic gates and latches are used in multi-phase clock generation, then clock signals can be generated, but robustness deteriorates and maximum frequency of operation is reduced
Solution Approach 1:
The invention replaces traditional logic gate-based phase generation with a sequential logic approach using D-type flip-flops. The flip-flops are clocked by the input clock signal and its inverted version, creating a deterministic state machine that generates consistent 90-degree phase shifts. This substitution eliminates the timing closure and phase swapping issues inherent in logic gate-based approaches, improving robustness and maximum operating frequency.
3Speed
If D-type flip-flop circuits or latches are avoided, then propagation delays are reduced, but the ability to generate multiple phase-shifted clock signals becomes more difficult
Solution Approach 1:
The circuit uses periodic clocking of D-type flip-flops with the input clock signal and its inverted version to generate phase-shifted outputs. By clocking different flip-flops at different phases of the input clock cycle (using both non-inverted and inverted clock signals), the circuit deterministically generates 4-phase and 8-phase clock signals with consistent 90-degree phase shifts, achieving high frequency operation without latches.
Data Source
AI summary
A circuitry for generating output clock signals with increasing phase delays comprises: an input receiving input clock signals with increasing phase delays, wherein the output clock signals are twice as many as the input clock signals; logic components connected in a loop with an output from a component connected as a first input to a following component, wherein the output is further connected as a second input to an oppositely positioned component; wherein each component receives the first, the second and a third input signal; wherein pairs of oppositely positioned components receive a common input clock signal and mask out the third input clock signal based on logic state of first and second input signals such that the outputs are phase shifted by 180 degrees; and wherein the circuitry outputs the output clock signals based on outputs from each component.