Multi-phase Clock Generation for Memory ISI Reduction
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Solution Overview
Problem
High frequency signal transmission in devices like memory devices faces challenges due to inter-symbol interference (ISI), which affects the accuracy of zero-crossing detection in differential interfaces, leading to inefficiencies in power consumption and cost.
Innovation Solution
A method and apparatus for receiving data using a 3-phase communication system that generates a clock signal by detecting transitions in the received sequence of symbols, delaying the symbols, and capturing previous symbols using a clock pulse, thereby reducing the impact of ISI and improving signal processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If differential interfaces are used for high frequency signal transmission, then common-mode rejection is provided for critical signals, but power consumption and cost increase significantly
Solution Approach 1:
The patent segments the signal transmission into multiple phases (first phase, second phase, third phase) with different clocking strategies. Critical signals receive full differential treatment with dedicated clock phases, while non-critical signals use simplified single-phase sampling, reducing overall power consumption while maintaining reliability for important data
Solution Approach 2:
Different quality levels of signal processing are applied locally to different signals based on their criticality. The system provides high-quality differential sampling with multiple clock phases for critical signals and lower-quality single-phase sampling for non-critical signals, optimizing the balance between reliability and power consumption
2Reliability
If differential interfaces are used for high frequency signal transmission, then common-mode rejection is provided for critical signals, but interface cost increases
Solution Approach 1:
The patent segments the interface architecture into hierarchical levels: full differential interfaces for critical signals and simplified single-ended or reduced-phase interfaces for non-critical signals. This segmentation reduces the total number of expensive differential interface components required while maintaining common-mode rejection where absolutely necessary
Solution Approach 2:
The system applies high-quality differential interface architecture only locally to critical signals that require common-mode rejection, while using cost-effective alternative architectures for non-critical signals, thereby optimizing the overall cost-performance ratio of the interface system
3Measurement precision
If zero-crossing detection is used in the presence of inter-symbol interference, then clock recovery is achieved, but detection accuracy deteriorates due to contributions from previous and following symbols
Solution Approach 1:
The patent applies equalization before zero-crossing detection by processing the received signal through an equalizer that compensates for inter-symbol interference from previous and following symbols. This preliminary action removes the harmful contributions before the critical zero-crossing detection occurs, significantly improving detection accuracy
Solution Approach 2:
The patent introduces an equalizer as an intermediary component between the received signal and the zero-crossing detector. This intermediary processes and cleanses the signal by removing inter-symbol interference effects, providing a cleaner input to the detector and thereby improving measurement precision
4Productivity
If multiple clock phases are used for sampling different signals, then data transmission capacity increases, but system complexity increases
Solution Approach 1:
The patent segments the clocking architecture into hierarchical levels: multiple clock phases are generated and applied only to critical signals requiring high data capacity, while non-critical signals use simpler single-phase or reduced-phase sampling. This segmentation increases productivity where needed while controlling overall system complexity
Solution Approach 2:
The system applies multi-phase clocking locally to specific critical signals rather than uniformly to all signals. This localized application of complex clocking architecture increases data transmission capacity for important data while avoiding unnecessary complexity in the overall system
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E~1F
AI summary
Systems and methods for multi-phase signaling are described herein. In one embodiment, a method for receiving data comprises receiving a sequence of symbols from a plurality of conductors (510), and generating a clock signal by detecting transitions in the received sequence of symbols (520). The method also comprises delaying the received sequence of symbols (522), and capturing one or more symbols in the delayed sequence of symbols using the clock signal, wherein a previous symbol in the delayed sequence of symbols is captured using a clock pulse in the clock signal generated based on a detected transition to a current symbol in the received sequence of symbols (530).