Multi-Phase Clock Sampling for Serial Data Recovery
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Solution Overview
Problem
The variability in the arrival time of read data and the wide range of clock signal periods in Mobile Pixel Link Level Zero (MPL Level-0) serial interfaces makes it challenging to sample read data accurately at the master device using a single static clock signal.
Innovation Solution
A system and method that utilize a clock generator to produce multiple out-of-phase clock signals, which are used by a read data recovery module and a phase selection module to recover read data by sampling at different times within a single period of the MC clock signal, allowing for the selection of the most appropriate phase for data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single static MC clock signal is used to sample read data, then the device complexity is reduced, but the measurement precision of data sampling deteriorates due to variable arrival times and wide clock period range
Solution Approach 1:
The patent transitions from a static single-clock signal to a dynamic multi-phase clock signal system. The clock generator produces multiple out-of-phase clock signals (e.g., 0°, 90°, 180°, 270°) that dynamically adapt to different sampling requirements, enabling accurate data recovery regardless of variable arrival times or clock period variations.
Solution Approach 2:
The sampling function is segmented into multiple parallel paths, each using a different clock phase. Instead of relying on a single sampling moment, the system divides the sampling task across multiple time phases, increasing the probability of capturing valid data even when arrival times vary.
2Measurement precision
If over-sampling using an internal clock with twice the frequency is used, then the measurement precision of data sampling is improved, but the device complexity and clock signal generation increase
Solution Approach 1:
Instead of changing the clock frequency (as in over-sampling with 2x frequency), the patent changes the clock phase parameter. Multiple clock signals with the same frequency but different phases (0°, 90°, 180°, 270°) are generated, achieving diverse sampling moments without increasing frequency complexity.
3Adaptability or versatility
If multiple out-of-phase clock signals are generated, then the adaptability of data recovery to variable timing is improved, but the device complexity increases
Solution Approach 1:
The clock generator produces periodic out-of-phase clock signals that cycle through defined phases (e.g., 0°, 90°, 180°, 270°). This periodic multi-phase approach provides regular, predictable sampling opportunities that adapt to variable timing conditions while maintaining implementable complexity through systematic phase generation.
Data Source
AI summary
A method for recovering data includes generating a plurality of out-of-phase clock signals. The method also includes generating samples of an incoming data signal, where a plurality of samples are generated using each of the plurality of clock signals. The method further includes selecting one of the plurality of clock signals and providing the samples generated using the selected clock signal. The incoming data signal may be received over a serial interface that includes a clock line for transporting a main clock signal. The out-of-phase clock signals could be approximately 0°, 90°, 180°, and 270° out-of-phase with respect to the main clock signal. The out-of-phase clock signals could be used to clock different registers that sample the incoming data signal. The selected clock signal could be selected by identifying a transition that occurs between samples associated with two of the clock signals and then selecting another of the clock signals.