Multi-Phase DFE Receiver Circuit for Higher PAM Baud Rates
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Solution Overview
Problem
Existing receiver circuits for pulse amplitude modulation (PAM) signaling face challenges in achieving high baud rates due to timing critical paths in decision feedback equalizer (DFE) circuits, particularly in processing higher levels of PAM modulation.
Innovation Solution
The proposed receiver circuit employs a plurality of decision feedback equalizer sub-circuits clocked by phase-offset divided clock signals, each operating at a fraction of the network frequency, utilizing speculative circuits and multi-baud cycles to reduce timing critical paths and improve processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single decision feedback equalizer circuit operates at network frequency, then timing accuracy is maintained, but processing frequency is limited and baud rate increases become difficult
Solution Approach 1:
The single DFE circuit is divided into multiple DFE sub-circuits (DFE0, DFE1, DFE2, DFE3) that operate in parallel. Each sub-circuit processes a different phase of the input signal, allowing the system to achieve higher effective processing frequency by combining results from all sub-circuits. This segmentation enables baud rate multiplication while keeping individual sub-circuit complexity manageable.
Solution Approach 2:
The solution introduces a time dimension by using multiple clock phases (phase 0, phase 1, phase 2, phase 3) to stagger the operation of different DFE sub-circuits. Instead of increasing the clock frequency of a single circuit, the system distributes processing across multiple time phases, effectively multiplying the processing throughput without proportionally increasing individual circuit complexity.
2Productivity
If the clock frequency is increased to achieve higher baud rates, then processing speed improves, but timing critical paths become more constrained and difficult to meet
Solution Approach 1:
The timing critical path is segmented across multiple DFE sub-circuits operating at the same clock frequency. Each sub-circuit has its own timing budget, and by distributing the overall processing across multiple phases, the system achieves higher effective baud rate without extending any single critical path beyond the original timing constraints.
Solution Approach 2:
The DFE sub-circuits perform their processing in advance during their assigned clock phases, preparing results that will be combined in subsequent phases. This preliminary action allows the system to maintain relaxed timing requirements for each individual sub-circuit while achieving high overall processing throughput.
3Speed
If multiple DFE circuits are used to increase processing frequency, then PAM signal processing frequency improves, but circuit complexity and resource requirements increase
Solution Approach 1:
Each DFE sub-circuit is designed as a universal, identical module that can process any phase of the input signal. This modular approach allows the system to scale processing capacity by simply replicating the same proven design rather than creating increasingly complex single circuits. The uniform structure reduces design complexity and facilitates easier implementation and verification.
Data Source
Figure 1a~1c
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AI summary
A receiver circuit that comprises a plurality of decision feedback equalizer sub-circuits, each associated with one of a plurality of divided clock signals. Each decision feedback equalizer sub-circuit is configured to receive PAM signalling that represents a current network symbol. Each one of the plurality of decision feedback equalizer sub-circuits is configured for sequential generation of an output symbol, and comprises: a first delay block that is configured to apply a delay to the PAM signalling in order to provide delayed PAM signalling, wherein the first delay block is clocked by the divided clock signal that is associated with the decision feedback equalizer sub-circuit; a coefficient application block; a slicer; and a second delay block that is configured to apply a delay to a DFE-sub-circuit output symbol from the slicer in order to provide an output symbol, wherein the second delay block is clocked by the divided clock signal that is associated with the decision feedback equalizer sub-circuit.