Multi-Phase Delay Locked Loop for Wider Memory Timing Margin
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Solution Overview
Problem
Conventional delay locked loop (DLL) circuits in semiconductor memory devices face reduced operation margin under high frequency operations or changes in conditions such as pressure, temperature, or input voltage, leading to decreased reliability when using a single-phase DLL output clock to control multiple control circuits.
Innovation Solution
A semiconductor memory device with a delay locked loop that generates multiple clocks and employs a phase control block to compare these clocks, generating phase control signals for a multi-phase delay control block to adjust clock delay compensation, thereby enhancing operation margin and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-phase DLL output clock is used to control multiple control circuits, then the device complexity is reduced, but the operation margin and reliability deteriorate under high frequency operations or changing conditions
Solution Approach 1:
The patent divides the single-phase DLL output clock into multiple phase clocks (first phase clock and second phase clock) using a phase control block. This segmentation allows different control circuits to use different phase clocks, improving operation margin and reliability under high frequency operations without significantly increasing overall system complexity.
2Ease of operation
If a single-phase DLL output clock is used, then the ease of operation is improved, but the adaptability to different operation conditions deteriorates
Solution Approach 1:
The patent introduces a dynamic phase control mechanism that can adjust the phase of output clocks based on operation conditions such as temperature, voltage, and frequency. The phase control block dynamically selects and outputs appropriate phase clocks to different control circuits, enabling the system to adapt to varying operation conditions while maintaining ease of operation through automated control.
3Reliability
If multiple phase clocks are generated and controlled, then the operation margin and reliability are improved, but the device complexity increases
Solution Approach 1:
The phase control block serves multiple functions: it generates multiple phase clocks, compares phases of input and output clocks, and distributes appropriate phase clocks to different control circuits. This multi-functionality reduces the need for separate circuits for each function, thereby improving reliability through multiple phase clocks while minimizing the increase in overall device complexity.
4Adaptability or versatility
If phase control signals are used to adjust clock delay, then the adaptability to operation conditions is improved, but the device complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where the phase control block compares the phase of the output clock with the input clock and generates phase control signals accordingly. This feedback-based phase adjustment enables the system to adapt to different operation conditions (temperature, voltage, frequency) automatically, improving adaptability while keeping the control circuit structure manageable through efficient feedback control.
Data Source
AI summary
A delay locked loop increases an operation margin of a delay locked loop by using an output clock having more advanced phase than a DLL output clock. A clock delay compensation block receives an external clock signal to thereby generate a first multi clock and a second multi clock. A phase control block compares the first multi clock with the second multi clock to generate phase control signal controlling a shifting operation. A multi-phase delay control block performs a shifting operation based on the phase control signal to control the clock delay compensation block.