Multi-phase Gate Driver for Slimmer Display Borders
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As display panel resolution increases, the number of conductive lines required in the peripheral area of LCD screens also increases, leading to a wider border, which is inefficient and aesthetically undesirable.
Innovation Solution
A multi-phase gate driver is implemented in the peripheral area of the display panel, featuring a start/end signal generator circuit and X shift register modules that generate delayed start and end signals, allowing the timing controller to output only one start and one end signal, reducing the number of conductive lines needed for signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of display panel is increased, then the image quality is improved, but the number of conductive lines in the peripheral area increases, resulting in a wider border
Solution Approach 1:
The gate driver is divided into multiple shift register modules (first shift register module, second shift register module, third shift register module, etc.) arranged in sequence. Each module handles a portion of the gate signals, allowing the system to support higher resolutions without proportionally increasing the border width. The segmentation distributes the signal generation load across multiple independent units.
Solution Approach 2:
The patent introduces a multi-phase clock signal system with N groups of clock signals (first clock signal, second clock signal, third clock signal, etc.), where each group has different phase delays. This adds a temporal dimension (phase timing) to the signal generation, allowing multiple gate signals to be controlled through phased clock cycles rather than requiring separate conductive lines for each signal.
2Adaptability or versatility
If the number of control signals is increased to support higher resolution, then the control capability is improved, but the number of conductive lines increases, leading to more complex circuit arrangement
Solution Approach 1:
Multiple shift register modules share common clock signal lines and control signal lines. Each module can generate gate signals independently using the same N groups of clock signals, allowing the system to achieve high-resolution control capability while reusing the same physical conductive lines across multiple modules, thereby reducing overall circuit complexity.
Solution Approach 2:
The system uses periodic clock signals with N different phases to control the shift register modules. Instead of requiring separate continuous control lines for each gate signal, the periodic phased clock signals enable time-multiplexed control, where the same physical lines are reused in different time phases to achieve complex control functionality.
Data Source
AI summary
A multi-phase gate driver includes a start/end signal generator circuit and X shift register modules. The start/end signal generator circuit is configured to sequentially output N start signals and N end signals according to a first control signal, a second control signal and N groups of clock signals. Each start and end signals have a delay relative to the previous one. Each group of clock signals includes a first clock signal and a second clock signal, which are inverted to each other. The X shift register modules are electrically coupled to the start/end signal generator circuit and each includes N shift register units. The Mth shift register unit of the first shift register module outputs a gate signal according to the Mth group of clock signals, the Mth start signal, and the gate signal outputted from the Mth shift register unit in the second shift register module.