Voltage-Mode Multi-Phase Interpolator for Low INL and DNL
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Solution Overview
Problem
Existing phase interpolators face challenges in generating equally spaced output clocks with reduced integral nonlinearity (INL) and differential nonlinearity (DNL), and they tend to have high standby power consumption.
Innovation Solution
The implementation of (m+1)-phase phase interpolators using voltage-mode phase interpolators, which include single-ended and differential configurations, with specific resistor and switch arrangements to generate output clocks that are equally spaced and have improved linearity, and the use of MOS transistors to control current flow between power supply branches, reducing INL and DNL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional phase interpolators are used to generate multi-phase clocks, then the output clocks can be generated, but the integral nonlinearity (INL) and differential nonlinearity (DNL) are high
Solution Approach 1:
The phase interpolator is divided into multiple independent voltage-mode phase interpolator circuits, each responsible for generating a specific phase output. This segmentation allows each circuit to be optimized independently, improving overall phase spacing precision while reducing INL and DNL through localized optimization of resistor and switch arrangements.
Solution Approach 2:
Different resistor values and switch configurations are applied to different phase interpolator circuits based on their specific phase requirements. Each circuit uses locally optimized component values to achieve precise phase spacing, thereby improving manufacturing precision while minimizing nonlinearity errors.
2Productivity
If conventional phase interpolators are used to generate multi-phase clocks, then the output clocks can be generated, but the standby power consumption is high
Solution Approach 1:
The voltage-mode phase interpolator circuits use periodic switching of MOS transistors to generate clock phases only when needed. During standby periods, the switching activity is minimized or halted, allowing the circuits to consume significantly less power while maintaining the capability to generate multi-phase clocks when required.
Solution Approach 2:
The circuit design allows for dynamic power management where power consumption is discarded (reduced) during standby modes and recovered (restored) when clock generation is needed. This is achieved through controlled switching of MOS transistors that can enter low-power states when not actively generating clock signals.
3Manufacturing precision
If voltage-mode phase interpolators with MOS transistors are used, then INL and DNL are reduced, but the circuit complexity increases
Solution Approach 1:
Multiple identical or near-identical voltage-mode phase interpolator circuits are used, each following the same standardized design with MOS transistors, resistors, and switches. This copying approach reduces design complexity by reusing proven circuit blocks while achieving precise phase spacing through replication of the optimized circuit architecture.
Solution Approach 2:
While the basic circuit topology remains consistent, specific parameters such as resistor values and MOS transistor dimensions are adjusted for each phase interpolator to achieve the desired phase spacing. This allows precision improvement through parameter optimization without fundamentally changing the circuit structure, thereby managing complexity.
Data Source
AI summary
A multi-phase phase interpolator receives two input clocks to generate several equally spaced output clocks using several phase interpolators. A phase interpolator may include a first circuit branch and a second circuit branch with output nodes that are connected together to provide an output clock. The output clock may be generated at least based on resistor values of the phase interpolator.