Multi-Phase PLL Clock Recovery for Stable High Data Rates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing chip-to-chip communication systems face challenges in maintaining stable and accurate clock signal recovery at high data rates due to transmission channel delays, interference, and noise, which affect the reliability and efficiency of data detection.
Innovation Solution
A Phase-Locked Loop (PLL) system that utilizes multiple phases of local and reference signals to generate a composite phase error signal through partial phase error signal summation, incorporating phase interpolators and charge pumps to improve loop stability and reduce jitter and noise immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional PLL system is used for clock signal recovery, then the system can operate at high data rates, but loop stability deteriorates and clock jitter increases due to transmission channel delays and noise
Solution Approach 1:
The patent divides the single phase error measurement into multiple phase error measurements by using multiple phases of local and reference signals. Each phase combination generates a partial phase error signal, which are then summed to create a composite phase error signal. This segmentation allows the PLL to maintain stability at high data rates by distributing the phase detection across multiple signal phases.
Solution Approach 2:
The patent extends the phase detection from a single-dimensional comparison to a multi-dimensional approach by utilizing multiple phases of both local and reference signals. This dimensional expansion creates a more comprehensive phase error measurement that improves loop stability and noise rejection while maintaining high-speed operation.
2Speed
If a conventional PLL system is used for clock signal recovery, then the system can operate at high data rates, but clock jitter increases due to interference and noise
Solution Approach 1:
The patent segments the phase error detection into multiple partial measurements, each comparing different phase combinations of local and reference signals. By summing these partial phase error signals, the system achieves a more accurate composite phase error measurement that reduces the impact of noise and interference, thereby reducing clock jitter at high data rates.
Solution Approach 2:
The patent implements an enhanced feedback mechanism where multiple phase error measurements are continuously summed and fed back to adjust the local oscillator phase. This multi-phase feedback approach provides more accurate and reliable phase correction, reducing clock jitter and improving timing accuracy at high-speed operation.
3Stability of the object's composition
If multiple phases of local and reference signals are used to generate composite phase error signal, then loop stability improves, but device complexity increases
Solution Approach 1:
The patent merges multiple partial phase error signals into a single composite phase error signal through summation. This combining approach consolidates the information from multiple phase comparisons into one unified error signal that can be processed by the existing PLL feedback mechanism, improving stability without requiring entirely new system architecture.
Solution Approach 2:
The patent makes the PLL system multi-functional by enabling it to process multiple phase signals simultaneously while maintaining compatibility with conventional single-phase PLL architectures. The same basic PLL components (phase comparator, loop filter, voltage-controlled oscillator) are used, but they now operate with enhanced multi-phase input processing, providing improved performance without proportionally increasing complexity.
4Reliability
If multiple phases of local and reference signals are used to generate composite phase error signal, then noise immunity improves, but device complexity increases
Solution Approach 1:
The patent segments the noise detection and rejection process into multiple phase-specific measurements. By comparing multiple phases and summing the resulting partial error signals, the system achieves better noise immunity as the random noise components tend to average out across the multiple measurements, while the systematic phase error information is reinforced.
Solution Approach 2:
The patent combines multiple partial phase error signals into a single composite signal that has improved signal-to-noise ratio. The merging process integrates the useful phase information from all phase comparisons while reducing the impact of random noise, achieving enhanced noise immunity through constructive combination of multiple measurements.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.