Multi-phase Sampling Circuit Mitigates Jitter and Skew
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Solution Overview
Problem
Conventional data sampling circuits face issues with jitter, skew, and pulse narrowing at high data speeds, leading to erroneous outputs due to metastability and inter-symbol interference, especially when set-up and hold times are violated.
Innovation Solution
The proposed solution involves a data sampling circuit that generates multiple samples of a data value at different phases of a clock signal, including early, nominal, and late samples, which are compared to a previously sampled value to determine the final data value, effectively widening the sample window and mitigating the effects of jitter and skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional single-phase sampling is used, then device complexity is low, but data sampling accuracy deteriorates at high speeds due to jitter and skew
Solution Approach 1:
The patent divides the sampling process into multiple phases (first sample phase, second sample phase, third sample phase) with different clock signals having different phase relationships. Each phase captures a sample at a different time offset, allowing the system to segment the sampling task across multiple lower-complexity operations rather than relying on a single high-precision sampling moment.
Solution Approach 2:
The patent introduces a temporal dimension by sampling at multiple different times relative to the data signal. Instead of attempting to capture the data at a single optimal moment, the system samples at multiple time points (early, nominal, late) and uses logic to determine the correct value, effectively adding a time dimension to the sampling process.
2Reliability
If multiple-phase sampling is implemented, then data sampling accuracy improves by widening the sample window, but device complexity increases
Solution Approach 1:
The patent segments the sampling process into three distinct phases with specific clock signals (CLK1, CLK2, CLK3) having different phase relationships. Each phase handles a specific portion of the sampling task, and the results are combined through logic circuitry, distributing the complexity across multiple simpler operations rather than one complex operation.
Solution Approach 2:
The patent uses feedback logic that compares the three sampled values and uses the previously latched data value to determine which sampled value should be used as the final output. This feedback mechanism automatically selects the correct sample based on the actual data transitions and timing conditions, improving reliability without requiring complex external control.
3Speed
If decision feedback equalization is used, then high speed operation is achieved, but vulnerability to jitter and skew remains
Solution Approach 1:
The patent segments the sampling process into multiple phases with different clock signals having different phase relationships. By sampling at multiple different times (early, nominal, late) and using logic to determine the correct value, the system segments the timing uncertainty across multiple samples, making the overall system more resistant to jitter and skew while maintaining high speed operation.
Data Source
AI summary
A circuit can include an input section configured to store a data signal in response to phase shifted clocks to generate a plurality of sample values; an output section configured to store one of the sample values; and a logic section configured to selectively output one of the sample values to the output section in response to the sample values and a previous sampled value stored in the output section.