Multi-phase SMPS Loop Phase Clocks for Transient Response
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Solution Overview
Problem
Existing multi-phase switching mode power supplies require high-frequency system clock signals for fast transient response, leading to high power consumption, complex chip process requirements, and large area usage.
Innovation Solution
A multi-phase SMPS system that generates N shifted phase clock signals from a system clock signal, forming loop phase clocks, to control switching circuits, allowing for low system clock frequency with short reaction time and high resolution, while reducing power consumption and chip process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-frequency system clock signal is used to achieve fast transient response, then transient response speed is improved, but power consumption increases
Solution Approach 1:
The patent divides the single system clock signal into N shifted phase clock signals distributed to N switching circuits. Each switching circuit operates independently with its own phase-shifted clock, enabling parallel processing and faster transient response without requiring a high-frequency system clock, thus reducing power consumption.
Solution Approach 2:
The patent introduces a spatial dimension by distributing N switching circuits across different phases instead of using a single high-frequency clock. The phase shift creates a temporal-spatial distribution where N circuits work in parallel with phase differences, achieving fast response without increasing clock frequency.
2Speed
If high-frequency system clock signal is used to achieve fast transient response, then transient response speed is improved, but chip process complexity increases
Solution Approach 1:
The patent segments the power supply into N independent switching circuits, each controlled by a phase-shifted version of the same low-frequency clock signal. This segmentation allows fast transient response through parallel operation while keeping the clock frequency low, simplifying chip process requirements.
3Speed
If high-frequency system clock signal is used to achieve fast transient response, then transient response speed is improved, but area usage increases
Solution Approach 1:
The patent divides the power supply circuit into N modular switching units that can be arranged in parallel. Each unit uses the same low-frequency clock signal with different phase shifts, enabling fast response through parallel processing while minimizing chip area by reusing the same clock signal infrastructure.
4Speed
If N switching circuits are controlled with phase-shifted clock signals, then transient response speed is improved, but control complexity increases
Solution Approach 1:
The patent pre-generates N phase-shifted clock signals using a dedicated clock signal generator before distributing them to the N switching circuits. This preliminary action of creating phase-shifted clocks simplifies the control logic in each switching circuit, as they only need to follow their assigned phase signal without complex inter-circuit coordination.
Solution Approach 2:
The patent introduces a clock signal generator as an intermediary component that creates N phase-shifted clock signals from a single input clock. This intermediary handles the complexity of phase shifting and signal distribution, allowing the switching circuits to operate simply by following their assigned phase signals.
Data Source
AI summary
A multi-phase SMPS has N switching circuits; a setting signal generator generating a setting signal based on an output signal of the SMPS; a clock signal generator generating a system clock signal; and a controller receiving the setting signal and the system clock signal, the controller generating N shifted phase clock signals according to the system clock signal, and the N shifted phase clock signals forming loop phase clocks, and the controller further generates N switching control signals based on the setting signal and the N shifted phase clock signals.