Multi-Phase TDC Sampling for Accurate Jitter Measurement

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Solution Overview

Problem

Existing USB communication systems face challenges in accurately measuring and screening jitter due to high-frequency clock requirements, which add complexity and uncertainty to on-die jitter measurement.

Innovation Solution

A multi-phase sampling technique using a ring oscillator with multiple taps and sampling circuits to reduce uncertainty in time-to-digital conversion by sampling the count signal at different phases, allowing for more accurate jitter measurement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If high-frequency clock operation is used for jitter measurement, then measurement precision is improved, but device complexity increases

Engineering Contradiction:
Improvejitter measurement precisionVSAvoidclock system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces a ring oscillator as an intermediary time-base source that operates at a lower frequency than traditional high-frequency clocks. This ring oscillator generates multiple phase-shifted clock signals that serve as mediators for sampling the enable period, thereby achieving high measurement precision without requiring complex high-frequency clock operation. The ring oscillator acts as a bridge between the simple low-frequency clock and the precise time measurement requirement.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If multi-phase sampling is implemented, then measurement precision is improved, but device complexity increases

Engineering Contradiction:
Improvetime-to-digital conversion precisionVSAvoidsampling circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the time measurement process into multiple discrete sampling operations. Instead of using a single high-frequency clock, the system divides the measurement into multiple lower-frequency sampling events using phase-shifted clock signals from different ring oscillator taps. Each sampling circuit captures the enable period at a different phase, and the final measurement is derived from combining these segmented measurements, thereby improving precision while keeping individual sampling circuits simple.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-dimension time measurement approach to a multi-dimensional approach by introducing phase as an additional dimension. Multiple sampling circuits operate simultaneously at different phases (0°, 120°, 240°) of the ring oscillator, creating a multi-dimensional sampling space. This allows the system to achieve higher measurement precision by exploiting the phase dimension without requiring higher clock frequencies.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Measurement precision

If ring oscillator with multiple taps is used, then measurement precision is improved, but ease of operation deteriorates

Engineering Contradiction:
Improvejitter measurement resolutionVSAvoidmeasurement process simplicity
Core Design Contradiction:
Measurement precisionVSEase of operation

Solution Approach 1:

The ring oscillator with multiple taps generates its own phase-shifted clock signals autonomously, eliminating the need for external complex clock distribution networks. The oscillator self-provides the multiple sampling clocks required for high-precision measurement, thereby improving measurement resolution while maintaining operational simplicity. The system essentially serves itself by generating its own measurement resources.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10965305B1Multi-phase sampling time-to-digital converter (TDC) for jitter measurement
Publication Date: 2021.03.30 QUALCOMM INC
  • US10965305B1 patent drawing
  • US10965305B1 patent drawing
  • US10965305B1 patent drawing

AI summary

Certain aspects are directed to a time-to-digital converter (TDC) that allows for a more accurate jitter measurement. The TDC generally includes a ring oscillator (RO) having a plurality of taps and configured to generate a plurality of RO signals at the plurality of taps, a counter having an input coupled to an oscillating node, and at least two sampling circuits, each having an input coupled to an output of the counter. In certain aspects, the at least two sampling circuits are configured to sample a count signal at the output of the counter based on at least two of the plurality of RO signals at the plurality of taps.