Multi-phase Timing Models for IC Design Closure
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Solution Overview
Problem
The complexity of designing integrated circuits with giga gate scale requires more accurate timing models to manage clock and data signal paths effectively, as existing methods often lead to overly pessimistic timing budgets and manual corrections, complicating the design process and limiting computer capacity.
Innovation Solution
The development of multi-phase timing models that accurately model max delay, false, and multi-cycle paths within partition blocks, allowing for synchronized clock and data path timing budgeting, enabling independent timing analysis between blocks and improving accuracy in timing analysis at the top level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If hierarchical partitioning is used to manage giga gate scale integrated circuit designs, then the complexity of evaluating overall circuit design is reduced and computer capacity limits are addressed, but the timing budget accuracy becomes overly pessimistic and manual corrections are required
Solution Approach 1:
The patent divides the integrated circuit design into hierarchical partitions (top level and multiple partition blocks) to manage giga gate scale complexity. Each partition can be analyzed independently with its own timing model, reducing the overall evaluation complexity while maintaining timing accuracy through phase-specific modeling of max delay, false, and multi-cycle paths.
Solution Approach 2:
The patent introduces multi-phase timing models that change the timing analysis parameters by separately modeling max delay paths, false paths, and multi-cycle paths within partition blocks. This parameter differentiation allows accurate timing budgeting at each hierarchical level without overly pessimistic estimates, eliminating the need for manual corrections.
2Measurement precision
If existing timing modeling methods are used for hierarchical partitions, then manual intervention and serialization are required for timing budget corrections, but this increases the design process complexity and reduces productivity
Solution Approach 1:
The patent enables automated timing budget generation for hierarchical partitions through multi-phase timing models. The system self-services by automatically analyzing max delay paths, false paths, and multi-cycle paths within partition blocks, generating accurate timing budgets without requiring manual intervention or iterative corrections, thus improving design process efficiency.
3Measurement precision
If synchronized clock and data path timing budgeting is implemented in hierarchical partitions, then timing analysis accuracy at top level is improved, but the device complexity and computational requirements increase
Solution Approach 1:
The patent applies local quality by implementing synchronized clock and data path timing budgeting specifically within partition blocks at lower hierarchical levels, where multi-phase timing models analyze max delay, false, and multi-cycle paths. This localized approach improves timing analysis accuracy at the top level without requiring complex synchronized modeling throughout the entire design, thus managing computational requirements effectively.
Data Source
AI summary
In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a first partition block for a top level of a hierarchical design of an integrated circuit; analyzing each pin of the first partition block for an attribute associated with the pin indicating a timing exception; and if a timing exception other than false path is indicated then generating an internal timing pin in a first timing graph model of the first partition block for each timing exception, and adding a timing arc and a dummy arc coupled to the internal timing pin in the first timing graph model of the first partition block. The internal timing pin adds a timing exception constraint for each timing exception. Timing of the top level may then be analyzed with the first timing graph model to determine if timing constraints, including the added timing exception constraints, are met.