Multi-Phase Wired Signaling for High-Density I/O
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Solution Overview
Problem
Current digital signaling and storage systems face limitations in increasing input/output capacity and bandwidth due to physical constraints and electromagnetic interference, with existing methods struggling to keep pace with growing data transfer demands and radiated emissions.
Innovation Solution
The implementation of a multi-phase wired signaling strategy that uses clusters of conductors to encode and decode digital data based on relative magnitudes of voltage/current signals, allowing for increased bit density and reduced radiated emissions without significant increases in power or chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-phase wired signaling is implemented, then input/output capacity and storage density are substantially increased, but device complexity increases due to the need for multiple conductors and signal processing circuitry
Solution Approach 1:
The patent transitions from traditional single-phase signaling to multi-phase signaling, adding the time dimension to signal transmission. By using multiple phases (e.g., 4-phase or higher) within a single I/O connection, the system encodes additional information dimensions, thereby increasing input/output capacity without proportionally increasing the number of physical conductors required.
Solution Approach 2:
The patent combines multiple signaling phases within a single I/O connection infrastructure. Instead of using separate connections for each data stream, the system merges multiple phases into unified signal paths, allowing multiple bits to be transmitted simultaneously through shared conductors and processing circuitry, thus reducing overall device complexity while maintaining high capacity.
2Reliability
If conventional differential-pair interconnections are used for high-speed data transfer, then electromagnetic interference and cross-coupling are reduced, but I/O capacity is limited because two connections are required for each I/O path
Solution Approach 1:
The patent segments the data transmission process into multiple phases, where each phase carries a portion of the data stream. By dividing the data into phased segments that can be transmitted simultaneously on shared I/O paths, the system achieves high I/O capacity without requiring separate differential pairs for each data bit, thus maintaining signal integrity while increasing throughput.
Solution Approach 2:
The patent implements continuous multi-phase signaling where data transmission occurs without interruption across multiple phases. This continuous action allows the I/O connections to be utilized more efficiently, maintaining high-speed data transfer capability while reducing the total number of connections needed, thereby increasing overall I/O capacity without sacrificing signal integrity.
3Speed
If higher frequency signals are used to increase data transfer rates, then bandwidth is increased, but electromagnetic interference and cross-coupling between signals increase
Solution Approach 1:
The patent employs periodic multi-phase signaling patterns to transmit data. By using periodic phase shifts (e.g., 90-degree increments) in a systematic sequence, the system achieves high data transfer rates through time-division multiplexing of data streams. This periodic action allows multiple signals to share the same physical medium without simultaneous transmission, thereby reducing electromagnetic interference and cross-coupling while maintaining high bandwidth.
Data Source
AI summary
Systems and methods for storing and/or communicating digital data associated with amplitudes and phases of a virtual periodic waveform having a designated period between components include, in one embodiment, circuitry that converts a first amplitude and a first phase to a first corresponding voltage or current and applies the first corresponding voltage or current to a first one of the plurality of components, such as conductors connecting integrated circuit chips or capacitors of a DRAM device, and converts the first amplitude and the first phase to (n−1) corresponding voltages or currents based on amplitudes of the periodic waveform phase shifted by about m*(360/n) relative to the first phase where m is indexed from one to (n−1) and applies each corresponding voltage or current to an associated component. Decoding is performed by comparing magnitudes of the component signals relative to one another rather that to a plurality of thresholds.