Multi-PHY DRAM Interface Selection for HBM3 and HBM4 Compatibility
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Solution Overview
Problem
The introduction of the HBM4 standard, which incorporates multiple physical interfaces, may render memory devices incompatible with existing HBM3 products, necessitating a solution for compatibility between different generations of High Bandwidth Memory (HBM) standards.
Innovation Solution
Incorporating a memory device with multiple physical interfaces and a setting circuit that allows selective connection to either one or both interfaces, enabling compatibility with both HBM3 and potential future standards by allowing the memory device to adapt to SoCs supporting one or multiple physical interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory devices are designed with multiple physical interfaces for HBM4 standard, then future compatibility and data processing speed are improved, but compatibility with existing HBM3 products deteriorates
Solution Approach 1:
The memory device is designed with multiple physical interfaces (first physical interface and second physical interface) that can selectively connect to different data input/output pins, enabling the same memory device to be compatible with both HBM3 products (single physical interface) and future HBM4 standards (multiple physical interfaces). This multi-functionality allows one device to serve multiple standards without requiring separate dedicated hardware for each standard.
Solution Approach 2:
The patent implements dynamic configurability through a setting circuit that can selectively connect the first physical interface to the first data input/output pin or the second physical interface to the second data input/output pin based on the required standard. This dynamic switching capability allows the memory device to adapt its interface configuration at runtime, resolving the contradiction between fixed hardware design and varying compatibility requirements.
2Adaptability or versatility
If memory devices use multiple physical interfaces, then adaptability to different SoCs is improved, but device complexity and configuration difficulty increase
Solution Approach 1:
The setting circuit is pre-configured with the capability to select between different physical interfaces and data input/output pin combinations before the memory device is put into service. This preliminary configuration approach allows the system to adapt to different SoC requirements without requiring complex runtime decisions or user intervention during operation, thereby maintaining ease of operation while achieving adaptability.
Data Source
AI summary
A memory device includes a first physical interface, a second physical interface, a first memory core, a second memory core, and a setting circuit. The first memory core is assigned to the first physical interface and includes a plurality of first stacked memory dies and connected via a through electrode. The second memory core is assigned to the second physical interface and includes a plurality of second stacked memory dies connected via a through electrode. The setting circuit sets at least one physical interface to be used for connection with an external device of the memory device among the first physical interface and the second physical interface.