Multi-PHY Memory Subsystem Ports for Bridge-Free Host Access
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Solution Overview
Problem
Conventional memory sub-systems face challenges in efficiently connecting multiple host systems due to the need for separate switches or bridge devices, which increase cost, power consumption, and latency, and are prone to single points of failure, while existing connections like PCIe cables have limited length and ethernet cables introduce additional costs and latency.
Innovation Solution
A memory sub-system that supports multiple physical interfaces (PHYs) and communication protocols, allowing host systems to connect directly without bridge devices by configuring multiple SR-IOV enabled ports based on host requirements, using a configuration space to identify suitable port configurations and lock them for stable connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate switches or bridge devices are used to connect multiple host systems to memory sub-systems, then connection flexibility is improved, but cost increases, power consumption increases, and latency increases
Solution Approach 1:
The patent merges multiple host system connections into a single memory sub-system by enabling multiple ports on the memory sub-system itself to function as switch fabric. This eliminates the need for external switch devices, directly reducing cost and device complexity while maintaining connection flexibility through configurable port assignments.
Solution Approach 2:
The memory sub-system is designed with multi-functional ports that can dynamically serve different host systems and memory devices based on configuration. Each port can be programmed to communicate with different targets, providing switch-like flexibility without requiring dedicated switch hardware, thereby reducing power consumption and cost.
2Adaptability or versatility
If separate switches or bridge devices are used to connect multiple host systems to memory sub-systems, then connection flexibility is improved, but latency increases
Solution Approach 1:
The patent extracts the switching function from external switch devices and integrates it directly into the memory sub-system architecture. By implementing switch fabric functionality within the memory sub-system itself, data can be routed between host systems and memory devices without external intermediaries, significantly reducing transmission latency while maintaining connection flexibility.
3Speed
If PCIe cables are used for connection, then data transfer speed is improved, but connection length is limited
Solution Approach 1:
The patent introduces multiple spatial dimensions for data transmission by providing multiple independent ports on the memory sub-system. Host systems can connect to different ports, creating parallel transmission paths that effectively extend the system's reach without requiring long individual cable runs. This multi-port architecture allows distributed hosting while maintaining high-speed PCIe connections over manageable distances.
4Length of stationary object
If ethernet cables are used for connection, then connection length is extended, but cost increases and latency increases
Solution Approach 1:
The patent employs configurable port parameters that allow the memory sub-system to adapt its communication characteristics. By adjusting port configuration parameters, the system can optimize for either high-speed short-distance PCIe connections or extended-range connections, flexibly adapting to different deployment scenarios without requiring ethernet infrastructure, thereby avoiding the associated cost and latency penalties.
Data Source
AI summary
A port configuration request is received from a host system of a plurality of host systems. The port configuration request comprises a plurality of port configurations each indicating a physical interface and a communication protocol for an interface port of the plurality of interface ports. An input/output (I/O) controller of each I/O function of a plurality of I/O functions associated with a respective interface port is configured to operate according to the communication protocol of the port configuration associated with the respective interface port for each interface port of the plurality of interface ports based on a port configuration of the plurality of port configurations associated with the respective interface port. A memory access command is executed using an I/O controller of an I/O function connected to the host system responsive to receiving the memory access command from a host system of the plurality of host systems.