Multi-Pin Parity Verification for Reliable Data Transmission
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Solution Overview
Problem
Existing data transmission verification methods using parity bits are prone to errors, leading to inaccuracies in data verification between electronic devices.
Innovation Solution
A data transmission parity device and method that utilizes a system with modules for acquiring, calculating, and determining signal values across multiple signal pins, applying modular operations, and controlling data reception based on parity bit comparisons to ensure accurate data transfer by identifying and repairing failed pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If data transmission verification is performed using a single parity bit, then the verification process is simple and quick, but the verification accuracy is low and prone to errors
Solution Approach 1:
The patent divides the verification process into multiple independent stages: acquiring signal values from multiple pins, calculating parity bits for different pin combinations, comparing calculated parity bits with received parity bits, and determining pin status based on comparison results. This segmentation allows each stage to be performed independently, improving verification accuracy while maintaining manageable system complexity
Solution Approach 2:
The patent transitions from single-parity-bit verification to multi-dimensional verification by using multiple signal pins (P1-P4) and multiple parity bits (P5-P8). Instead of verifying data through a single parity check, the system performs verification across multiple dimensions (different pin combinations), thereby significantly improving verification accuracy and error detection capability
2Reliability
If multiple signal pins and parity bits are used for verification, then verification accuracy improves, but the complexity of the verification system increases
Solution Approach 1:
The patent designs the verification system to perform multiple functions: acquiring signal values from data pins, calculating parity bits for different pin combinations, comparing calculated parity bits with received parity bits, and determining the status of individual pins. This multi-functional approach allows a single system to handle various verification tasks, improving reliability while avoiding the need for separate dedicated systems for each function
Solution Approach 2:
The system implements feedback by comparing the calculated parity bits with the received parity bits and using the comparison results to determine pin status. When discrepancies are detected, the system can identify which specific pins have failed and trigger appropriate error handling mechanisms. This feedback loop ensures high reliability by continuously monitoring and verifying data transmission integrity
Data Source
AI summary
A device using parity for verification of data transmitted from a first device through a data line to a second device includes a processor and a memory. The data line includes first to fourth pins for transmitting data and fifth to eighth pins for transmitting parity information. The processor receives values of first to eighth pins, calculates sum of the values of combinations of the first to fourth pins for data and applies modular operations on results of the four combinations. Equality or non-equality with the parity values of the fifth to eighth pins is determined, and the second device is permitted to receive the data when the results correspond, the modular operation being a (mod 2) operation. A method applied to such device is also disclosed.