Multi-Pitch Gate Configuration for Logic and RF Transistor Layouts
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Solution Overview
Problem
Advanced integrated circuits face challenges with shrinking feature sizes, leading to issues such as overlay shift, contact to gate bridging, increased parasitic capacitance, and reduced alignment margins, particularly in three-dimensional transistors like FinFETs and gate-all-around FETs, which affect performance and reliability.
Innovation Solution
A semiconductor circuit structure with field-effect transistors featuring multi-pitch gates tailored for different functional blocks, such as logic and high-frequency devices, utilizing different gate pitches, dimensions, and dummy gates to enhance performance and reliability by compensating for etch loading effects and improving fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are shrunk to advance integrated circuit technology, then device density and integration capability are improved, but overlay shift, contact to gate bridging, parasitic capacitance, and alignment margins deteriorate
Solution Approach 1:
The gate structure is segmented into multiple pitch regions with different gate pitches. First gates with a first pitch are formed for logic circuits, while second gates with a second pitch (different from the first pitch) are formed for high-frequency circuits. This segmentation allows each region to be optimized independently for its specific function while maintaining overall manufacturing precision.
Solution Approach 2:
Different gate pitch dimensions are applied to different functional blocks based on their specific requirements. Logic circuit blocks use one gate pitch optimized for density, while high-frequency circuit blocks use another gate pitch optimized for performance. This local quality approach ensures that each region has the optimal characteristics for its intended function.
2Area of stationary object
If gate pitch is reduced to increase packing density, then area utilization is improved, but parasitic capacitance and circuit timing issues worsen
Solution Approach 1:
The patent applies different gate pitches to different functional blocks: smaller gate pitches in logic circuit regions to maximize packing density, and larger gate pitches in high-frequency circuit regions to minimize parasitic capacitance. This local optimization allows each block to achieve its optimal performance characteristics.
Solution Approach 2:
The gate structure is divided into multiple segments with different pitch characteristics. First gates serve logic functions with optimized density, while second gates serve high-frequency functions with optimized timing. This segmentation resolves the contradiction by allowing different pitch values in different functional regions.
3Reliability
If three-dimensional transistors like FinFETs are used to enhance device performance, then device performance is improved, but alignment margins and source/drain region size are reduced
Solution Approach 1:
The patent changes the gate pitch parameter to compensate for the reduced alignment margins inherent in three-dimensional transistor structures. By adjusting the gate pitch based on the transistor type and functional block requirements, the overall alignment robustness is improved while maintaining the performance benefits of FinFETs and other 3D structures.
4Manufacturing precision
If dummy gates are added to compensate for etch loading effects, then fabrication uniformity is improved, but device complexity increases
Solution Approach 1:
The dummy gates serve multiple functions: they compensate for etch loading effects to improve fabrication uniformity, and they also define functional blocks with specific pitch characteristics. This multi-functionality reduces the need for additional separate structures, thereby limiting the increase in device complexity.
Data Source
AI summary
The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.