Multi-Plane Embedded Devices in Fanout Wafer Packaging
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Solution Overview
Problem
Conventional fanout wafer level packaging (FO-WLP) devices face challenges in increasing device density due to miniaturization limits, leading to larger footprints as the number or complexity of embedded components increases, necessitating a solution to enhance packaging efficiency.
Innovation Solution
The implementation of a substrate with a cavity (SwC) structure that allows for multiple planes of microelectronic devices, with conductive through-substrate vias (TSVs) and a redistribution layer to facilitate electrical connections between embedded devices and external contact pads, enabling higher device density within a given footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number or complexity of embedded components is increased, then device functionality is improved, but device footprint increases
Solution Approach 1:
The patent transitions from a single-plane device layout to a multi-plane embedded device architecture. By stacking multiple planes of microelectronic devices vertically within the molded package body and providing access to both top and bottom surfaces, the invention utilizes the third dimension (vertical space) to increase device density and functionality without proportionally increasing the horizontal footprint.
2Quantity of substance
If multiple planes of microelectronic devices are integrated, then device density is increased, but manufacturing complexity increases
Solution Approach 1:
The patent divides the package into multiple discrete planes or layers, each containing microelectronic devices. This segmentation allows for independent fabrication and assembly of each plane, which can then be stacked and interconnected. The segmentation approach simplifies the manufacturing process compared to attempting to create a monolithic multi-plane structure, as each plane can be processed separately using standard wafer-level packaging techniques.
Solution Approach 2:
The patent implements a nested structure where multiple planes of devices are stacked one within another in the vertical dimension. Each plane is essentially nested within the package body, with devices on different planes accessible from different surfaces. This nesting approach maximizes the use of vertical space to achieve high device density while maintaining a compact overall package footprint.
3Reliability
If contact pads are distributed over a large surface area, then electrical connectivity is improved, but device footprint increases
Solution Approach 1:
The patent redistributes contact pads across multiple planes and surfaces (top and bottom) rather than concentrating them on a single large surface. By providing access to both top and bottom surfaces of the package and distributing contact pads across different vertical levels, the invention achieves comprehensive electrical connectivity while maintaining a compact horizontal footprint.
Data Source
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AI summary
A packaged semiconductor structure includes an interconnect layer and a first microelectronic device on a first major surface of the interconnect layer. The structure also includes a substrate having a cavity, wherein the cavity is defined by a vertical portion and a horizontal portion, wherein the vertical portion surrounds the first device, the horizontal portion is over the first device, and the first device is between the horizontal portion and the first major surface of the interconnect layer such that the first device is in the cavity. The structure further includes a second microelectronic device attached to the horizontal portion of the substrate, and encapsulant on the interconnect layer and surrounding the first device, the substrate, and the second device, such that the substrate is embedded in the encapsulant.