Multi-Plane Leadframe for Dual-Side Semiconductor Cooling

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Solution Overview

Problem

Semiconductor packages face challenges in effectively cooling power semiconductor dies due to limited heat dissipation methods, particularly in maintaining efficient thermal management across both sides of the package.

Innovation Solution

A leadframe design with multiple die pads and contact pads arranged in distinct planes allows for dual-side cooling, where the upper surface of one die pad and the lower surface of another form part of the outer package surface, enabling heat dissipation from both sides during the molding process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If a conventional leadframe with single-plane die pads is used, then the manufacturing process is simple, but heat dissipation from both sides of the package is not achieved

Engineering Contradiction:
Improveheat dissipation efficiencyVSAvoidleadframe structure complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The leadframe structure transitions from a conventional single-plane configuration to a multi-plane three-dimensional arrangement. Specifically, the leadframe includes a first die pad in a first plane and a second die pad in a second plane that is offset from the first plane, creating dual-side cooling surfaces that enable heat dissipation from both the top and bottom of the semiconductor package.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The leadframe is segmented into multiple functional components arranged in different planes: a first die pad for mounting a first semiconductor die, a second die pad for mounting a second semiconductor die, and contact pads for electrical connections. This segmentation allows each component to serve its specific function while collectively achieving dual-side thermal management.

Inventive Principle:
Principle #1Segmentation

2Reliability

If dual-side cooling is implemented with multiple die pads in different planes, then thermal management is improved, but the leadframe structure becomes more complex

Engineering Contradiction:
Improvethermal management effectivenessVSAvoidleadframe structural complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The leadframe structure serves multiple functions simultaneously: it provides mechanical support for semiconductor dies, establishes electrical connections through contact pads, and enables thermal management from both sides of the package. The multi-plane configuration of die pads allows the same leadframe structure to fulfill both electrical and thermal management roles efficiently.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Temperature

If additional manufacturing steps are added to achieve dual-side cooling, then heat dissipation improves, but manufacturing complexity and cost increase

Engineering Contradiction:
Improvecooling efficiencyVSAvoidmanufacturing process simplicity
Core Design Contradiction:
TemperatureVSEase of manufacture

Solution Approach 1:

The dual-side cooling capability is built into the leadframe structure during its initial formation, before the semiconductor packaging process begins. The multi-plane die pad configuration is pre-established in the leadframe design, so that when molding compound is applied and semiconductor dies are mounted, dual-side cooling is automatically achieved without requiring additional post-processing steps or specialized molding techniques.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10840172B2Leadframe, semiconductor package including a leadframe and method for forming a semiconductor package
Publication Date: 2020.11.17 INFINEON TECHNOLOGIES AG
  • US10840172B2 patent drawing
  • US10840172B2 patent drawing
  • US10840172B2 patent drawing

AI summary

A leadframe, that is to be incorporated into a semiconductor housing is provided. The leadframe may include a first die pad, a second die pad and a plurality of contact pads. A lower surface of the contact pads and a lower surface of the first die pad are arranged in a first plane. An upper surface of the second die pad is arranged in a second plane distant from the first plane by an overall thickness of the semiconductor package.