Multi-Plane Memory Read Command Simplification
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Solution Overview
Problem
Current memory systems face inefficiencies in multi-plane read operations due to complex command sequences, leading to increased processing time and potential bottlenecks in data output, especially as the number of planes increases.
Innovation Solution
A simplified command approach is implemented, where the controller provides page read commands with target page addresses, buffers data in page buffers, and then outputs data using either an all-plane data output command or respective-plane data output commands, reducing the need for multiple address-specific commands and minimizing clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple address-specific data output commands are provided for each plane, then data can be output from each plane, but the number of commands increases and processing time increases
Solution Approach 1:
The patent combines multiple address-specific data output commands into a single all-plane data output command that can trigger simultaneous data output from multiple planes. This merging of commands eliminates the need to issue separate commands for each plane, thereby reducing the total number of commands and the associated processing time while maintaining the ability to output data from all planes.
Solution Approach 2:
The all-plane data output command is designed to serve multiple planes simultaneously with a single command. This universal command structure allows the memory device to output data from any combination of planes without requiring plane-specific addressing in the data output phase, making the command system more versatile and efficient.
2Productivity
If complex command sequences are used for multi-plane read operations, then data can be read from multiple planes, but the processing time increases and bottlenecks occur
Solution Approach 1:
The patent implements preliminary action by having the memory device buffer data from multiple planes in advance during the page read command phase. This pre-buffering allows the data to be ready for output before the all-plane data output command is issued, eliminating the need for sequential data retrieval and reducing the overall processing time while maintaining high data read throughput.
Solution Approach 2:
The patent ensures continuity of useful action by overlapping the data buffering process with the command execution phase. While the memory device is buffering data from multiple planes, the controller can prepare and issue the all-plane data output command, ensuring that no time is wasted between data preparation and data output, thereby maintaining continuous productive operation.
3Loss of time
If simplified commands are used, then processing time is reduced, but the ability to specify target pages may be limited
Solution Approach 1:
The patent applies segmentation by separating the address specification function into two distinct phases: the page read command phase where target pages are specified, and the data output phase where simplified all-plane commands are used. This segmentation allows the system to maintain full address specification capability when needed while using simplified commands for the data output operation, thus resolving the contradiction between time efficiency and adaptability.
Data Source
AI summary
An operating method of a memory system that includes a memory device including a plurality of planes and a plurality of page buffers for the plurality of planes, respectively, and a controller suitable for controlling the memory device, the operating method includes: providing, by the controller, the memory device with page read commands for respective target planes among the plurality of planes; simultaneously reading, by the memory device, data from the target planes and buffering the data in target page buffers corresponding to the respective target planes in response to the page read commands; selectively providing, by the controller, the memory device with an all-plane data output command or respective-plane data output commands from which target page addresses are omitted; and sequentially outputting, by the memory device, the data buffered in the target page buffers, in response to the all-plane data output command or the respective-plane data output commands.