Multi-Plane Nonvolatile Memory With Decoder Between Substring Groups
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Solution Overview
Problem
Current nonvolatile semiconductor memory devices face challenges in achieving high-density memory cell integration per unit area, particularly in three-dimensional structures, where the integration of peripheral circuits with memory cell arrays is inefficient, leading to limitations in memory density and performance.
Innovation Solution
The implementation of a Cell On Peri (COP) structure in a multi-plane configuration, where each plane includes cell strings orthogonal to the semiconductor layer, with dedicated decoders, page buffer circuits, and peripheral circuits connected via conductive layers, allowing for efficient operation voltage supply and data management across multiple planes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional structure with memory cell arrays is used to increase memory cell integration per unit area, then memory density is improved, but the integration of peripheral circuits with memory cell arrays becomes inefficient
Solution Approach 1:
The patent implements a Cell On Peri (COP) structure where peripheral circuits are disposed in a material plane between the memory cell array plane and the underlying substrate. This vertical stacking approach transitions from planar integration to three-dimensional integration, allowing peripheral circuits to be positioned in the depth dimension rather than competing for lateral space, thereby maintaining high memory cell density while enabling efficient peripheral circuit integration.
Solution Approach 2:
The patent divides the memory device into multiple independent planes: a first plane containing memory cell arrays and a second plane containing peripheral circuits. Each plane can be independently designed, fabricated, and controlled. This segmentation allows optimal layout for memory cells in one plane while accommodating peripheral circuits in another plane, resolving the integration efficiency problem without compromising memory density.
2Productivity
If multiple planes with dedicated decoders and peripheral circuits are implemented, then voltage control and data management efficiency are improved, but device complexity increases
Solution Approach 1:
The patent implements shared conductive layers that serve multiple functions: they provide electrical connections between peripheral circuits and memory cell arrays, supply operation voltages to multiple planes, and facilitate data transfer between different planes. This multi-functionality reduces the need for separate dedicated structures for each function, thereby improving productivity while controlling overall device complexity.
Solution Approach 2:
The patent combines the functions of voltage supply, data transfer, and circuit control into integrated decoder circuits that operate across multiple planes. The first decoder supplies operation voltages to the first plane while the second decoder supplies voltages to the second plane, with both decoders connected through shared conductive layers. This merging of functions improves data programming and reading efficiency by enabling coordinated operation across planes while managing complexity through unified control architecture.
Data Source
AI summary
A nonvolatile memory device includes a memory cell array including cell strings stacked in a direction orthogonal to a substrate and including a first substring group and a second substring group dividing the cell strings, and an address decoder connected to memory cells of the cell strings via a plurality of word lines and configured to provide operating voltages to the memory cells, wherein the address decoder is disposed between the first substring group and second substring group.