Multi-Plane Memory Descriptor for Bad Block Handling
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Solution Overview
Problem
Conventional memory sub-systems face performance degradation and increased latency due to the need for multiple descriptors for multi-plane operations, especially when dealing with bad blocks, which require individual command sequences, leading to increased overhead and resource consumption.
Innovation Solution
A memory sub-system that enables full multi-plane operation by issuing a single descriptor for multiple commands, where commands associated with good blocks are duplicated to replace those of bad blocks, allowing parallel operations across multiple blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple descriptors are issued for multi-plane operations to handle bad blocks, then reliability is improved, but device complexity and overhead increase
Solution Approach 1:
The patent applies copying by duplicating command sequences from good blocks to replace those associated with bad blocks. Instead of creating entirely new descriptors for bad blocks, the system copies existing valid command sequences and modifies them, reducing the complexity of handling bad blocks while maintaining reliability.
Solution Approach 2:
The patent changes parameters by modifying command sequences to include plane identification and block status information. By encoding bad block handling instructions within the existing descriptor framework rather than creating separate descriptor structures, the system maintains reliability while reducing device complexity.
2Reliability
If individual command sequences are issued for each bad block, then reliability is improved, but access time and latency increase
Solution Approach 1:
The patent merges multiple individual command sequences into a single unified descriptor that can handle both good and bad blocks simultaneously. By combining what would otherwise be separate operations into one coordinated descriptor, the system maintains data integrity through proper error handling while significantly reducing access latency by eliminating sequential processing overhead.
Solution Approach 2:
The patent performs preliminary action by pre-identifying and marking bad blocks before multi-plane operations commence. Command sequences are pre-configured with alternatives for bad blocks, allowing the system to handle errors without interrupting the overall operation flow, thus maintaining reliability while minimizing time loss.
3Reliability
If multiple descriptors are used for multi-plane operations, then comprehensive error handling is achieved, but resource consumption increases
Solution Approach 1:
The patent makes the descriptor structure universal by designing it to handle both good and bad blocks within a single framework. The same descriptor type and command sequence structure serve multiple functions - normal operations for good blocks and error handling for bad blocks - eliminating the need for separate specialized descriptors and reducing overall resource consumption while maintaining comprehensive error handling capability.
4Productivity
If conventional multi-plane operation is implemented, then parallel processing capability is achieved, but overhead from multiple descriptors reduces efficiency
Solution Approach 1:
The patent merges multiple descriptor management tasks into a unified descriptor structure that coordinates multi-plane operations. By combining what would otherwise be separate descriptor entities into one integrated structure, the system maintains parallel processing capability while dramatically reducing the overhead associated with creating, managing, and coordinating multiple separate descriptors.
Data Source
AI summary
Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.