Multi-Plane Memory Page Detection via Parallel Word Line Sensing
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Solution Overview
Problem
Existing methods for identifying the last non-erased memory page in electronic memory devices are inefficient due to their high time complexity, particularly when subjected to stringent timing constraints, as they rely on binary search techniques with a complexity of order log2 N, where N is the number of logical word lines.
Innovation Solution
A device and method that divide word lines into R>2 contiguous sub-ranges and assign a subset of word lines to boundaries across P=R−1 memory planes, allowing for parallel sensing of programmed or erased states, reducing the search range by a factor of P/R in each iteration until a configured condition is met.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If binary search techniques are used to identify the last non-erased memory page, then the search can be performed systematically, but the time complexity is high (order log2 N) and latency is increased
Solution Approach 1:
The patent divides the memory word lines into multiple sub-ranges and assigns different subsets of word lines to different memory planes. This segmentation allows parallel searching across multiple planes simultaneously, reducing the overall search time from O(log2 N) to approximately O(log2(N/P)) where P is the number of planes, thereby resolving the time complexity issue while maintaining manageable algorithmic complexity
Solution Approach 2:
The patent introduces a new dimension of parallelism by utilizing multiple memory planes (P=R-1 planes) to perform simultaneous searches. By mapping word line subsets to different planes and conducting parallel sensing operations, the solution transforms a sequential one-dimensional search into a multi-dimensional parallel search, significantly reducing initialization latency
2Productivity
If the search range is reduced by a factor of P/R through parallel operations, then initialization time is reduced, but the device structure becomes more complex with multiple planes and sub-range assignments
Solution Approach 1:
The patent creates a universal search mechanism that can operate across multiple memory planes using the same fundamental sensing operations. The controller is designed to handle arbitrary numbers of planes (P=R-1) and sub-ranges (R), making the solution scalable and adaptable to different memory configurations without requiring fundamentally different approaches for each plane count
Solution Approach 2:
The patent employs dynamic assignment of word line subsets to different memory planes based on the chosen subdivision factor R. The system can adaptively adjust how word lines are partitioned and assigned to planes, allowing flexible optimization of search performance while managing complexity through configurable parameters rather than fixed rigid structures
Data Source
AI summary
A memory device includes logic to detect the last page written in multi-plane non-volatile memory. The device includes a memory array, and a storage controller. The memory array includes multiple planes and multiple word lines operable on the memory array. The storage controller is configured to divide the word lines into contiguous sub-ranges and assign a subset of the word lines to boundaries of the sub-ranges. Each word line of the subset of word lines is assigned to a page in a different one of the memory planes. The controller operates the subset of word lines to sense a page programmed or erased state from each of the memory planes in parallel.