Multi-Plane Memory Programming With Defective-Plane Disablement
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Solution Overview
Problem
Multi-plane memory devices experience decreased programming efficiency and increased program disturbance when defective memory planes are repeatedly programmed, affecting normal memory planes.
Innovation Solution
A method for programming multi-plane memory devices that involves applying a program pulse to memory cells, verifying their state, and disabling a plane if a preset number of cells fail to reach a predetermined state after multiple attempts, thereby reducing program disturbance and accelerating data programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-plane memory device programs two or more memory planes simultaneously, then programming efficiency is enhanced, but when defective memory planes are present, programming speed decreases and program disturbance increases in normal memory planes
Solution Approach 1:
The patent applies preliminary verification action by verifying the program state of memory cells after each programming attempt before proceeding to the next plane. This preliminary check identifies defective planes early, preventing wasted programming cycles on planes that cannot be successfully programmed, thus maintaining high programming efficiency while avoiding the slowdown caused by repeatedly attempting to program defective planes.
2Reliability
If defective memory planes are repeatedly programmed, then attempt is made to program data into defective planes, but programming speed decreases and program disturbance increases in normal memory plane
Solution Approach 1:
The patent extracts and isolates defective memory planes from the simultaneous programming process. By verifying the program state of each plane and identifying those that fail to reach the predetermined state, the system separates defective planes from the normal programming workflow. This extraction prevents defective planes from causing program disturbance to normal planes and eliminates wasted programming cycles, thereby maintaining high programming speed.
3Productivity
If multiple memory planes are programmed simultaneously, then programming efficiency is enhanced, but program disturbance increases in normal memory plane when defective planes are present
Solution Approach 1:
The patent implements feedback control by continuously monitoring the program state of memory cells in each plane after programming attempts. The verification step provides feedback on whether each plane has been successfully programmed or is defective. Based on this feedback, the system adjusts the programming process by disabling defective planes and continuing with only functional planes, thereby preventing program disturbance to normal planes while maintaining high programming efficiency through selective simultaneous programming.
Data Source
AI summary
A memory device includes a plurality of planes. A method of programming the memory device includes applying a first program pulse to one or more memory cells of a first plane of the plurality of planes, verifying whether each one of the memory cells reaches a predetermined program state, and in response to a preset number of the memory cells in the first plane failing to reach the predetermined program state after the memory cells being verified for a predetermined number of times, disabling the first plane when applying a second program pulse after the first program pulse.