Concurrent Multi-Plane Memory Block Erase for Higher Throughput
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Solution Overview
Problem
Existing memory devices face significant throughput impacts due to the time-consuming nature of single-block erase operations, particularly in low density universal flash storage devices, where erasing a single memory block contributes a substantial portion of the overall operating time.
Innovation Solution
A multi-block erase operation is executed concurrently on multiple memory blocks, applying a series of erase pulses to target memory cells across multiple memory blocks and planes, reducing the throughput impact and erase time overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If single-block erase operations are used, then memory device simplicity is maintained, but throughput is significantly impacted and erase time overhead increases
Solution Approach 1:
The patent combines multiple single-block erase operations into a single multi-block erase operation that can concurrently erase multiple memory blocks across different memory planes. This merging of operations reduces the total erase time overhead and improves throughput by approximately 50% compared to sequential single-block erases, while the controller manages the complexity through unified command handling
2Duration of action of moving object
If single-block erase operations are used, then operation simplicity is maintained, but erase time overhead increases substantially
Solution Approach 1:
The patent extends the erase operation from a single memory plane to multiple memory planes simultaneously, adding a dimensional aspect to the erase process. This multi-plane concurrent erase capability reduces the total erase time by performing erases in parallel across different planes, while the controller abstracts the complexity through standardized multi-plane erase commands
3Productivity
If multi-block erase operations are implemented, then throughput improves by approximately 50%, but operation complexity increases
Solution Approach 1:
The patent creates a universal erase operation that can handle both single-block and multi-block erases across multiple memory planes through a unified command interface. The controller implements multi-functionality by managing concurrent erase operations on different memory blocks and planes using standardized protocols, thereby improving throughput while keeping the interface simple for the host system
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-block erase operation significantly reduces the throughput impact by approximately 50% compared to single-block erase operations, enhancing memory sub-system performance by concurrently erasing a larger portion of the memory array.
Implementation Method 1
causes a set of erase pulses to be applied to a first set of target memory cells of a first memory block and a second set of target memory cells of a second memory block concurrently
Data Source
AI summary
A memory sub-system to initiate an erase operation to erase a first set of memory cells of a first memory block of a first memory plane and a second set of memory cells of a second memory block of a second memory plane of a memory device. A set of erase pulses of the erase operation are caused to be applied to the first set of memory cells of the first memory block and the second set of memory cells of the second memory block concurrently. One or more erase verify sub-operations of the erase operation are executed to verify the first set of memory cells and the second set of memory cells are erased.