Multi-Plane Semiconductor Memory Parallel Programming
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Solution Overview
Problem
The existing semiconductor memory devices with only two planes face limitations in increasing density and operating speed due to the sequential input of program data, which restricts the efficiency of program operations.
Innovation Solution
The semiconductor memory device is enhanced by incorporating at least four planes, allowing for simultaneous input of program data to page buffers and parallel processing, with a method that includes sequential input of program data to selected pages, performing program operations, and verifying operations across multiple planes, enabling efficient data storage and reduced operation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If only two planes are used in the memory device, then the device complexity is reduced, but the data density and operating speed are limited
Solution Approach 1:
The memory device is divided into multiple independent planes (first plane and second plane), each capable of performing program operations simultaneously. This segmentation allows parallel data storage operations, increasing overall data density and operating speed without requiring a single monolithic structure.
Solution Approach 2:
The patent transitions from a single-plane architecture to a multi-plane architecture, adding the dimension of parallel plane operation. By introducing a second plane that can operate independently and simultaneously with the first plane, the system achieves higher data density and faster operation speeds.
2Device complexity
If program data is input sequentially into page buffers for two planes, then the device complexity is minimized, but the time required for program operations increases
Solution Approach 1:
Program data is pre-loaded into page buffers of both planes before the program operation begins. The first page buffer receives program data for the first plane while the second page buffer simultaneously receives program data for the second plane, eliminating sequential data input delays and enabling parallel operation.
Solution Approach 2:
The patent enables continuous parallel program operations across both planes by maintaining page buffers in both planes ready for simultaneous data input. This continuous useful action eliminates idle waiting time between plane operations, significantly reducing total program operation time.
3Ease of manufacture
If only two planes are used, then the manufacturing cost is reduced, but the productivity and operating speed are limited
Solution Approach 1:
The memory device is segmented into multiple independently manufacturable plane modules. Each plane can be manufactured and tested separately before being integrated into the final device, maintaining ease of manufacture while enabling parallel operations that significantly improve productivity and operating speed.
Data Source
AI summary
A semiconductor memory device is operated by, inter alia, sequentially inputting program data to page buffers coupled to selected pages of at least four planes in order to program selected memory cells included in the selected pages; performing a program operation on each of the four planes; performing a program verify operation on each of the four planes; and inputting new program data for next pages to the page buffers coupled to the next pages, after determining the selected pages of at least two of the four planes have passed the program verify operation, while performing the program operations and the program verify operations on the two remaining planes.