Multi-Plane Memory with Plane Ready Signals
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Solution Overview
Problem
Traditional memory operation command protocols restrict simultaneous access to multiple memory planes, as they prohibit issuing new commands to non-operating planes until current operations in other planes are completed, limiting concurrent data access and operation efficiency.
Innovation Solution
The implementation of a memory system with multiple memory planes, each equipped with a plane ready (PRDY) and array ready (PARDY) signal, allowing for selective execution of memory commands based on the status of these signals, enabling asynchronous independent plane operations (AIPO) and synchronous chip operations (SCO), thereby allowing overlapping access to different planes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory operation command protocols are used to ensure proper operation control, then reliability is maintained, but productivity deteriorates due to prohibition of simultaneous access to multiple planes
Solution Approach 1:
The memory system is divided into multiple independent memory planes, each with its own ready status signals (PRDY and PARDY). This segmentation allows each plane to be controlled and accessed independently, enabling concurrent operations across different planes while maintaining proper control protocols for each individual plane.
Solution Approach 2:
The patent implements feedback mechanisms through ready status signals (PRDY and PARDY) that continuously report the operational state of each memory plane. This feedback enables the system to dynamically determine which planes are available for new operations, allowing concurrent access to non-busy planes while maintaining reliability by preventing operations on busy planes.
2Reliability
If current operations in one plane are completed before issuing new commands to other planes, then reliability is maintained, but loss of time increases due to sequential operation execution
Solution Approach 1:
The system maintains continuous useful action by allowing new operations to be issued to memory planes that are not currently busy. The ready status signals enable the system to continuously utilize available planes, eliminating idle wait times and ensuring that processing capacity is maximized at all times.
Solution Approach 2:
The patent enables preliminary actions by allowing operations to be prepared and issued to planes in advance, as long as those planes are in a ready state. This eliminates the need to wait for current operations to complete before preparing next operations, thereby reducing overall execution time while maintaining reliability.
3Device complexity
If new commands are prohibited to non-operating planes, then device complexity is reduced through simplified protocols, but productivity deteriorates due to limited concurrent access
Solution Approach 1:
The patent applies local quality by implementing plane-specific ready status signals (PRDY and PARDY) for each memory plane. This allows the system to maintain simple, consistent control protocols at the local plane level while enabling complex concurrent operations at the system level by independently managing the state of each plane.
Data Source
AI summary
A method of operating a memory comprising a plurality of memory planes is disclosed. Each memory plane includes at least one corresponding memory array. The method includes, for each memory plane of the plurality of memory planes, generating (i) a corresponding plane ready (PRDY) signal indicating a busy or a ready state of the corresponding memory plane, and (ii) a corresponding plane array ready (PARDY) signal indicating a busy or a ready state of the corresponding memory array of the corresponding memory plane, such that a plurality of PRDY signals and a plurality of PARDY signals are generated corresponding to the plurality of memory planes. Execution of a memory command for a memory plane of the plurality of memory planes is selectively allowed or denied, based on status of one or more of the plurality of PRDY signals and the plurality of PARDY signals.