Multi-Plane Memory Device Parallel Read Control
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Solution Overview
Problem
Current memory devices are limited in their ability to perform multiple read operations efficiently across different memory planes, leading to potential bottlenecks in data access and processing speeds.
Innovation Solution
A memory device with a control circuit capable of performing multiple read operations on various memory planes at different speeds, allowing for simultaneous and optimized read operations across multiple planes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple read operations are performed on different memory planes, then data processing efficiency is improved, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple independent memory planes, each capable of performing read operations independently. The control circuit is segmented to handle different planes separately, allowing parallel read operations while maintaining manageable complexity through modular architecture.
Solution Approach 2:
The patent introduces the dimension of multiple memory planes stacked vertically, transforming a single-plane sequential access architecture into a multi-plane parallel access architecture. This dimensional expansion enables simultaneous read operations across different planes without proportionally increasing control circuit complexity.
2Ease of operation
If read operations are performed at different speeds on different planes, then system responsiveness is improved, but control complexity increases
Solution Approach 1:
The control circuit is designed with dynamic speed adjustment capability, allowing each memory plane to operate at different read speeds based on system requirements. This dynamic control enables flexible performance optimization while the modular architecture keeps the control complexity manageable through independent plane control.
Solution Approach 2:
The patent changes the operational parameter of read speed independently for each memory plane. By allowing different read speeds (e.g., fast read for one plane, normal read for another), the system can optimize responsiveness for different data access patterns without requiring a complete redesign of the control architecture.
Data Source
AI summary
A memory device includes: memory cells of first and second planes; and a control circuit suitable for performing multiple read operations on the memory cells in response to a read command. The multiple read operations may include a first read operation which is performed on the memory cells of the first plane in a first read period and a second read operation which is performed on the memory cells of the second plane in a second read period.