3D Semiconductor Memory Layout With Multi-Plane Source Routing
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Solution Overview
Problem
The degree of arrangement freedom of lines in three-dimensional semiconductor memory devices is limited, which restricts the efficient use of area and complicates the manufacturing process.
Innovation Solution
A semiconductor memory device is designed with a multi-plane structure, including first and second memory cell arrays and circuit groups, where the second memory cell array overlaps a substrate with a wider metal source pattern, and a common source line is formed at a temperature of 450° C or less to improve line arrangement freedom and operational reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional three-dimensional semiconductor memory device structure is used, then memory cells can be arranged in three dimensions to reduce area, but the degree of arrangement freedom of lines is limited
Solution Approach 1:
The patent introduces a multi-plane structure where memory cell arrays are arranged in different planes (first plane and second plane) with different orientations. The first memory cell array extends in a first direction while the second memory cell array extends in a second direction intersecting the first direction. This dimensional arrangement allows lines to be routed more freely across multiple planes, significantly increasing the degree of arrangement freedom while maintaining compact three-dimensional memory cell packing.
2Area of stationary object
If multiple memory cell arrays and circuit groups are arranged in limited area, then area efficiency is improved, but line arrangement freedom is restricted
Solution Approach 1:
The patent divides the memory device into multiple independent planes, with each plane containing specific memory cell arrays and circuit groups. The first plane includes the first memory cell array and first circuit group, while the second plane includes the second memory cell array and second circuit group. This segmentation allows each plane to be designed and routed independently, simplifying the overall line arrangement complexity while achieving high area efficiency through vertical stacking of multiple planes.
3Ease of manufacture
If common source line is formed using conventional materials and processes, then manufacturing is straightforward, but operational reliability is limited due to higher resistivity
Solution Approach 1:
The patent changes the material parameter of the common source line from conventional silicon-based materials to metal materials with lower resistivity. The common source line is formed using metal layers (such as aluminum or copper) that provide significantly lower electrical resistance compared to silicon. This parameter change improves operational reliability by reducing voltage drops and power consumption, while the metal layers are integrated into the existing multi-plane structure using standard semiconductor manufacturing processes.
Data Source
AI summary
A semiconductor device includes: a substrate extending in a first direction and a second direction intersecting with the first direction; a plurality of input/output pads disposed at one side of the substrate; a first circuit adjacent to the input/output pads in the first direction; a second circuit disposed to be spaced farther apart from the input/output pads in the first direction than the first circuit; a first memory cell array overlapping the first circuit; a second memory cell array overlapping the second circuit; first metal source patterns overlapping the first memory cell array and being spaced apart from each other in the second direction; and a second metal source pattern overlapping the second memory cell array and formed to have a width wider than a width of each of the first metal source patterns in the second direction.