Multi-Plane NAND Memory Data Transfer Automation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory sub-systems face inefficiencies in multi-plane read operations for non-volatile memory devices, as they require dedicated commands from the memory sub-system controller, leading to resource consumption and latency issues as the number of planes increases.
Innovation Solution
Implementing a multi-plane sense operation scheme that allows NAND memory devices to automatically initiate data transfer from cache registers without dedicated commands, eliminating the need for change read column commands and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dedicated commands are used to transfer data from cache registers in multi-plane read operations, then data transfer can be controlled by the memory sub-system controller, but controller resources are consumed and latency increases as the number of planes increases
Solution Approach 1:
The memory device is configured to automatically transfer data from cache registers of multiple planes to the memory sub-system controller without requiring dedicated change read column commands from the controller for each plane. The memory device self-manages the data transfer process, eliminating the need for continuous controller intervention and reducing command latency.
Solution Approach 2:
The data transfer function is extracted from the memory sub-system controller and transferred to the memory device itself. The memory device now handles the automatic data transfer from its own cache registers, removing this task from the controller's responsibility and reducing controller resource consumption.
2Productivity
If dedicated change read column commands are issued for each plane, then data can be transferred from each cache register, but the number of commands increases with the number of planes leading to resource consumption
Solution Approach 1:
Multiple data transfer operations that were previously separate (one command per plane) are merged into a single automated process. The memory device combines the data transfer from all plane cache registers into one unified operation triggered by a single read command, reducing command sequence complexity.
Solution Approach 2:
The memory device is designed with universal data transfer capability that handles multiple planes through a single command interface. The automated transfer mechanism serves all planes uniformly, making the system more versatile and reducing the need for plane-specific command sequences.
Data Source
AI summary
A method includes transferring data out of a first buffer coupled to a first plane of a plurality of planes of a memory component, where the data was previously transferred from the first plane to the first buffer responsive to an access request to sense data stored in the plurality of planes of the memory component. The method further includes transferring, subsequent to transferring the data out of the first buffer and independently of a command from a processing device, data out of a second buffer coupled to a second plane of the plurality of planes of the memory component, where the data transferred out of the second buffer was previously transferred from the second plane to the second buffer responsive to the access request.